Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Having enclosed cavity
Patent
1998-03-30
1999-03-16
Picardat, Kevin M.
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Having enclosed cavity
438455, 438460, H01L 2130, H01L 2146
Patent
active
058829865
ABSTRACT:
Starting with a semiconductor wafer of known type including an internal, planar p-n junction parallel to major surfaces of the wafer, one of the wafer surfaces is covered with a masking layer of silicon nitride. A plurality of intersecting grooves are then sawed through the masking layer for forming a plurality of mesas having sloped walls with each mesa including a portion of the planar p-n junction having edges which intersect and are exposed by the mesa walls. The groove walls and exposed junction edges are glass encapsulated in a process including heating the wafer. The masking layers are then removed in a selective etching process not requiring a patterned etchant mask, and the now exposed silicon surfaces at the top of the mesas, as well as the opposite surface of the wafer, are metal plated. The wafer is then diced along planes through the grooves for providing individual chips each having a glass passivated mesa thereon.
REFERENCES:
patent: 5489554 (1996-02-01), Gates
patent: 5723360 (1998-03-01), Iwasaki
patent: 5759753 (1998-06-01), Namba et al.
patent: 5759872 (1998-06-01), Van Roijen et al.
patent: 5760482 (1998-06-01), Van Aken
Amato John E.
Chan Joseph Y.
Einthoven Willem G.
Eng Jack
Garbis Dennis
Collins Devon
General Semiconductor Inc.
Picardat Kevin M.
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