Semiconductor chip with a plurality of scannable storage...

Details Semiconductor chip with a plurality of scannable storage... Semiconductor chip with a plurality of scannable storage...

2011-08-09

2011-08-09

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07996738

ABSTRACT:
A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.

REFERENCES:
patent: 7165006 (2007-01-01), Dhong et al.
patent: 7269780 (2007-09-01), Arima et al.
patent: 7346820 (2008-03-01), Padhye et al.
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patent: 7469372 (2008-12-01), Nardini et al.
patent: 7580807 (2009-08-01), Bullock et al.
patent: 2005/0010832 (2005-01-01), Caswell et al.
patent: 2009/0019329 (2009-01-01), Aitken et al.

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