Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-12-12
2006-12-12
Soward, Ida M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S001000, C257S002000, C257S003000, C257S004000, C257S005000, C257S006000, C257S007000, C257S008000, C257S216000, C257S348000, C257S349000, C257S350000, C257S351000, C257S352000, C257S353000, C257S354000, C257S507000
Reexamination Certificate
active
07148543
ABSTRACT:
A semiconductor chip includes a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.
REFERENCES:
patent: 5399507 (1995-03-01), Sun
patent: 5740099 (1998-04-01), Tanigawa
patent: 5777362 (1998-07-01), Pearce
patent: 5796125 (1998-08-01), Matsudai et al.
patent: 5894152 (1999-04-01), Jaso et al.
patent: 5973366 (1999-10-01), Tada
patent: 6037199 (2000-03-01), Huang et al.
patent: 6037202 (2000-03-01), Witek
patent: 6180486 (2001-01-01), Leobandung et al.
patent: 6214653 (2001-04-01), Chen et al.
patent: 6333532 (2001-12-01), Davari et al.
patent: 6350653 (2002-02-01), Adkisson et al.
patent: 6413857 (2002-07-01), Subramanian et al.
patent: 6429488 (2002-08-01), Leobandung et al.
patent: 6465846 (2002-10-01), Osanai
patent: 6528853 (2003-03-01), Christensen et al.
patent: 6555891 (2003-04-01), Furukawa et al.
patent: 6835981 (2004-12-01), Yamada et al.
patent: 10-0210626 (1999-07-01), None
patent: 2001-0003206 (2001-01-01), None
Mizushima Ichiro
Nagano Hajime
Nitta Shinichi
Oyamatsu Hisato
Sato Tsutomu
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Soward Ida M.
LandOfFree
Semiconductor chip which combines bulk and SOI regions and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor chip which combines bulk and SOI regions and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor chip which combines bulk and SOI regions and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3661577