Semiconductor chip stack structure

Details Semiconductor chip stack structure Semiconductor chip stack structure

2005-12-20

2005-12-20

Vu, Hung (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S686000, C257S692000, C257S778000

Reexamination Certificate

active

06977439

ABSTRACT:
Semiconductor chip stack structure and method are provided. A first chip has a first metal bump formed on a first electrode pad. The first chip is attached to and electrically connected to a substrate. The electrical connection is made by a bump reverse bonding method in which one end of a bonding wire is ball-bonded to the substrate and the other end is stitch-bonded to the metal bump. The second chip is stacked on the first chip. The bonding wire is substantially parallel with a top surface of the first chip. Accordingly, the chip stack structure and method minimize a space between the first chip and the second chip, thereby reducing the total height of semiconductor chip stack.

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English language abstract for Japanese Publication No. 06-021328.
English language abstract for Japanese Publication No. 08-288455.
English language abstract for Japanese Publication No. 2000-307057.
English language abstract for Japanese Publication No. 10-116849.

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