Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – On insulating carrier other than a printed circuit board
Reexamination Certificate
1998-05-19
2001-06-26
Tran, Minh Loan (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
On insulating carrier other than a printed circuit board
C257S778000, C257S650000, C257S692000, C257S784000
Reexamination Certificate
active
06252298
ABSTRACT:
BACKGROUND OF THE INVENTION
1 Field of the Invention
The present invention relates generally to a semiconductor device. More particularly, the present invention relates to a semiconductor chip package in which an active surface of a semiconductor chip is attached to a bottom surface of a flexible circuit board having a central opening, and in which input/output pads on the active surface of the chip are electrically connected to a circuit layer on a top surface of the flexible circuit board through the opening, so that the package can be reduced to a size on the order of that of the chip.
2 Description of the Prior Art
As semiconductor integrated circuit (IC) chips become increasingly sophisticated, the component density increases as does the number of input/output (I/O) pads per chip, resulting in larger chips. However, there is a continuing need to reduce the size of the semiconductor chip package to meet the need for smaller devices.
One of the packages that has been developed to meet this need is a ball grid array (BGA) package. The BGA package provides a relatively high surface-mount density and improved electrical performance as compared to a conventional plastic package. A distinct difference in the structure of the BGA package from the conventional plastic package is that the electrical interconnection between the semiconductor chip and a mother board is provided by a printed circuit board (PCB) having circuit patterns and solder balls instead of a lead frame.
The typical BGA package
10
is illustrated in FIG.
1
. As shown in
FIG. 1
, the chip
11
is attached to the top surface of the PCB
12
. The circuit patterns
13
on the top surface of the PCB
12
extend to the bottom surface through vias
15
. The circuit patterns
13
on the top surface are electrically connected to the chip
11
by bonding wires
14
, while those on the bottom surface are electrically connected to the mother board (not shown) by solder balls
16
. Parts of the top surface of the PCB
12
, the chip
11
, and the bonding wires
14
are encapsulated by resin
17
. The body of the PCB
12
is generally made of FR-4, FR-5, or BT (Bismaleimide triazine) resin. FR-4 and FR-5 are fire retardant epoxy glass-reinforced laminates.
The BGA package
10
is larger than the chip
11
because the PCB
12
used in the BGA package
10
requires an area without circuit patterns
13
to allow the chip
11
to be attached to the PCB
12
. Furthermore, the width and the distance between adjacent circuit patterns
13
are limited to 70 &mgr;m, respectively. Therefore, it is difficult to manufacture a BGA package when circuit patterns
13
having a small width or a small degree of spacing there between are required.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor chip package of a size on the order of that of the semiconductor chip itself.
It is another object of the present invention to provide a semiconductor chip package employing a circuit board with fine circuit patterns.
It is still another object of the present invention to provide a semiconductor chip package which, by its design, prevents liquid resin from overflowing during the manufacture thereof.
It is still another object of the present invention to provide a semiconductor chip package in which the upper surface of an encapsulant is disposed below the upper surface of terminals.
It is still another object of the present invention to provide a semiconductor chip package having a coefficient of thermal expansion similar to that of a mother board.
The present invention achieves these and other objects by providing a semiconductor chip package which comprises a semiconductor chip having an active surface, and a plurality of I/O pads extending across central parts of the active surface. The package also includes a flexible circuit board having an electrically non-conductive flexible tape with a top surface, a bottom surface and a central opening therein. A circuit layer is patterned on the top surface of the flexible tape. The circuit layer has a plurality of circuit traces, bonding pads to which first ends of the traces are connected, and land pads to which the other ends of the traces are connected.
The active surface of the semiconductor chip is attached to the bottom surface of the flexible tape, so that the I/O pads on the chip are exposed through the opening of the flexible tape. Accordingly, a plurality of metal bonding wires are electrically interconnect the I/O pads and the bonding pads through the opening. Furthermore, the flexible circuit board can have an area nearly equal to that of the semiconductor chip. In other words, the present invention can provide a so-called chip sized package (CSP).
The I/O pads, the bonding pads, and the metal wires in the package of the invention are all encapsulated. A plurality of terminals are provided on and are electrically connected to the land pads on the top surface of the flexible tape. A polyimide tape is preferably used as the flexible tape of the invention.
The circuit layer may include multilayered circuit traces in which upper circuit traces are disposed over lower circuit traces with an insulating layer being interposed therebetween.
The encapsulant may be provided by a method of supplying liquid resin having a certain viscosity into the opening and over the bonding pads. A dispenser is preferably used for the supplying the resin. Moreover, the package may comprise a dam extending on the top surface of the flexible tape radially outward of the bonding pads and around the opening, so that the dam will prevent the liquid resin from overflowing as it is supplied onto the bonding pads. The dam may be also formed by a method similar to that used to form the encapsulant.
The encapsulant extends a first predetermined distance from the circuit layer, and each terminal extends a second predetermined distance from the circuit layer, the first predetermined distance preferably being less than the second predetermined distance.
The flexible circuit board may further include a protective layer on the top surface of the flexible tape so as to protect the circuit traces. In addition, the protective layer may have a groove extending between the bonding pads and the land pads. The aforementioned dam can be provided in the groove and rise above the protective layer so that the dam will prevent the liquid resin, used to form the encapsulant, from overflowing. A polyimide layer is preferably used as the protective layer.
The flexible circuit board may also further include a stiffener on the bottom surface of the flexible tape. The stiffener can be made of a material having the same coefficient of thermal expansion as that of a mother board to which the package will be mounted. Moreover, the flexible circuit board may further include an adhesive layer between the stiffener and the semiconductor chip. The adhesive layer can be made of an electrically non-conductive adhesive material, such as silicone resin or a nonsilicone resin having a low modulus of elasticity.
REFERENCES:
patent: 4996587 (1991-02-01), Hinrichsmeyer et al.
patent: 5583375 (1996-12-01), Tsubosaki et al.
patent: 5650593 (1997-07-01), McMillan et al.
patent: 5674785 (1997-10-01), Akram et al.
patent: 5677566 (1997-10-01), King et al.
patent: 5866949 (1999-02-01), Schueller
patent: 6013946 (2000-01-01), Lee et al.
Choi Wan Gyun
Lee Kyu Jin
Jones Volentine, P.L.L.C.
Samsung Electronics Co,. Ltd.
Thai Luan
Tran Minh Loan
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