Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Outside periphery of package having specified shape or...
Patent
1997-11-10
2000-10-31
Clark, Sheila V.
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Outside periphery of package having specified shape or...
257692, 257686, 257724, H01L 2304
Patent
active
061407003
ABSTRACT:
The semiconductor chip package includes a package body with a recess and a plurality of barrier parts formed along one side thereof. Each of the barrier parts has a first region and a second region projecting from the first region, and adjacent first regions are separated by a slot. A semiconductor chip, including a reference surface having a circuit and a plurality of bonding pads formed thereon, is disposed in the recess of the package body. A conductive member is disposed in each slot, and a connecting member, associated with each bonding pad, electrically connects the associated bonding pad with a corresponding conductive member. A sealing member seals the semiconductor chip, the connecting members, and at least a portion of the conductive members in contact with the connecting members. Stacking these packages in the transverse and/or longitudinal direction further reduces their mounting area and increases the integrated capacity per unit of mounting area.
REFERENCES:
patent: 3489956 (1970-01-01), Yani et al.
patent: 4672151 (1987-06-01), Yamamura
patent: 5377077 (1994-12-01), Burns
patent: 5574314 (1996-11-01), Okada et al.
Clark Sheila V.
LG Semicon Co. Ltd.
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