Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2001-06-20
2002-09-03
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S786000, C257S784000, C257S738000, C257S737000, C257S668000, C257S774000, C257S684000, C257S796000, C257S673000, C257S678000, C257S680000, C257S788000
Reexamination Certificate
active
06445077
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is directed to a semiconductor chip package for a semiconductor chip with center and edge bonding pads and a manufacturing method of such semiconductor chip package.
Plastic package, in which a semiconductor chip is attached to a leadframe and encapsulated with a molding compound, is not effective in decreasing the footprint and the profile of the package. Accordingly, to implement a small-footprint and low profile semiconductor device, semiconductor packaging techniques using a PCB (Printed Circuit Board) or a tape instead of the leadframe have been developed. An example of the newly developed packages is a BGA (Ball Grid Array) package. The BGA package has a semiconductor chip mounted and connected to a PCB, and then encapsulated. External terminals, such as solder balls, are attached to the other side of the PCB, so that bonding pads of the semiconductor chip connect to corresponding external terminals. A smaller version of the BGA package is called a fine pitch BGA.
FIG. 1
is a cross-sectional view of a conventional fine pitch BGA package
110
. In fine pitch BGA package
110
, beam leads
122
of a tape
121
connect to bonding pads
112
of a semiconductor chip
111
. (Only one of bonding pads
112
are shown in
FIG. 1.
) An elastomer
125
is interposed between semiconductor chip
111
and tape
121
, and a molding part
135
serves to protect semiconductor chip ill and beam leads
122
from the external impact. Solder balls
137
are attached to tape
121
, and thereby electrically connected to corresponding bonding pads
112
of semiconductor chip
111
.
Semiconductor chip
111
has its bonding pads the center of semiconductor chip
111
. However, when more bonding pads are necessarily to be formed on a semiconductor chip, the bonding pads can be formed along both the center and edges of the semiconductor chip. Semiconductor chip package
110
cannot package a semiconductor chip having both center and edge bonding pads. Accordingly, a semiconductor chip package that can package such semiconductor chip needs to be developed.
SUMMARY OF THE INVENTION
In accordance with an aspect the present invention, a semiconductor chip package includes a semiconductor chip and a substrate on which the semiconductor chip attaches. The semiconductor chip includes center bonding pads formed on a surface of the semiconductor chip in a central area of the surface and edge bonding pads formed along edges of the surface of the semiconductor chip. The substrate includes a first window that exposes the center bonding pads, a second window that exposes the edge bonding pads, connection pads around the first and second windows, external terminal pads, and a wiring pattern that connects the connection pads to the external terminal pads.
The semiconductor chip package further includes bonding wires, an encapsulation body, and external terminals formed on the external terminal pads of the substrate. The bonding wires connect the center and edge bonding pads of the semiconductor chip to the connection pads of the substrate. The encapsulation body encapsulates side surfaces of the semiconductor chip, a portion of the bottom surface of the substrate, the bonding wires, and the connection pads. The encapsulation body includes a first encapsulation portion and a second encapsulation portion. The first encapsulation portion encapsulates the side surfaces of the semiconductor chip and the portion of the bottom surface of the substrate, and the second encapsulation portion encapsulates the bonding wires and the connection pads.
In the package, the center bonding pads can be aligned in parallel with or in perpendicular to the edge bonding pads. In addition, the first and second windows can be integrated into a single window.
Another aspect of the invention provides a method for manufacturing a semiconductor chip package. The method includes: preparing a semiconductor chip having center bonding pads and edge bonding pads; preparing a substrate, which includes a first window, a second window, connection pads around the first and second windows, external terminal pads, and a wiring pattern; attaching the semiconductor chip on the substrate such that the first window exposes the center bonding pads and the second window exposes the edge bonding pads; connecting the first and second bonding pads of the semiconductor chip to corresponding connection pads of the substrate; encapsulating side surfaces of the semiconductor chip, a portion of the bottom surface of the substrate, the bonding wires, and the connection pads; and forming external terminals on the external terminal pads of the substrate.
The encapsulating includes a first encapsulation of the side surfaces of the semiconductor chip and a portion of the bottom surface of the substrate and a second encapsulation of the bonding wires and the connection pads. The first encapsulation is performed by potting. The second encapsulating is performed by potting or by transfer-molding.
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Choi Ill Heung
Song Young Hee
Flynn Nathan J.
Greene Pershelle
Samsung Electronics Co,. Ltd.
Skjerven Morrill LLP
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