Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-03
2001-01-16
Loke, Steven H. (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000, C438S257000, C438S258000, C438S261000, C438S262000, C438S266000, C257S369000
Reexamination Certificate
active
06174758
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the fabrication of a semiconductor device. More specifically, the present invention relates to a method of fabricating a semiconductor device that includes a fieldless array having salicide gate electrodes.
BACKGROUND OF THE INVENTION
In many memory applications, memory transistors and conventional CMOS devices are fabricated on a single semiconductor wafer. Typically, the CMOS devices are fabricated in a first region of the wafer, while the memory transistors are fabricated in a second region of the wafer. On some wafers, the memory transistors are fabricated as part of a fieldless array. A fieldless array is defined as an array that does not use field oxide to isolate the various elements of the array. Because field oxide is not required to isolate the memory transistors in a fieldless array, the memory transistors can be laid out with a relatively high density.
In certain applications, conventional CMOS devices (e.g., transistors) are fabricated in the second region, but do not form part of the fieldless array. That is, the CMOS devices located in the second region are isolated by field oxide. Thus, the second region can include both memory transistors and CMOS devices.
In order to distinguish the above-described transistors, the following nomenclature will be used. As used herein, the term “logic transistor” refers to a transistor fabricated in accordance with conventional CMOS processes, regardless of whether the transistor is fabricated in the first region or the second region of the semiconductor wafer. A CMOS logic transistor is isolated from other elements by field oxide. CMOS logic transistors can further be classified as high voltage CMOS logic transistors and low voltage CMOS logic transistors. High voltage CMOS logic transistors have a thicker gate oxide than low voltage CMOS logic transistors, thereby enabling the high voltage CMOS logic transistors to withstand higher gate voltages. The term “fieldless array transistor” refers to a transistor that does not require field oxide isolation. For example, floating gate type non-volatile memory transistor are often used to form a fieldless array.
The process steps required to fabricate high and low voltage CMOS logic transistors are not fully compatible with the process steps required to fabricate fieldless array transistors. As a result, relatively complex processes would be required to form the high and low voltage CMOS logic transistors and the fieldless array transistors on the same wafer. It would therefore be desirable to have an efficient process for fabricating high and low voltage CMOS logic transistors and fieldless array transistors on the same wafer.
In addition, it may be difficult to achieve an acceptable yield when fabricating both CMOS logic transistors and fieldless array transistors on the same wafer. For example, it is anticipated that methods for fabricating the gate electrodes of the fieldless array transistors may result in electrical short circuits between the source and drain regions of the fieldless array transistors. These short circuits may exist for the following reason. During the formation of the CMOS logic transistors, an etch is performed to create the sidewall spacers of the CMOS logic transistors. This etch can expose the silicon between the source and drain regions of the fieldless array transistors. To reduce the resistance of the gate structures of the transistors, a refractory metal is subsequently deposited over the upper surface of the wafer to form self aligned silicide or “salicide” gate electrodes. A silicide layer is formed by reacting this refractory metal with exposed silicon. Thus, a silicide layer forms between the source and drain regions of the fieldless array transistors thereby causing a short circuit. It would therefore be desirable to have a method for fabricating CMOS logic transistors having self aligned silicide gate structures and fieldless array transistors on the same wafer.
SUMMARY
Accordingly, the present invention provides efficient processes for fabricating CMOS logic transistors having self aligned silicide gate structures and fieldless array transistors on the same wafer. Specifically, in one embodiment of the present invention a semiconductor device comprises at least one logic transistor and a plurality of fieldless array transistors. Both the logic transistor and the fieldless array transistors have gates composed of a polysilicon layer having a metal silicide layer formed thereon. In addition, the logic transistors have drain and source regions having metal silicide active regions formed thereon in a self aligned manner. In one embodiment, the source and drain regions of the fieldless array transistors are buried bit lines with overlying bit line oxide. In this embodiment, the fieldless array transistors can be nonvolatile memory cells having a floating gate structure. The floating gate structures can comprise, for example, a nitride layer sandwiched between two oxide layers.
In accordance with another embodiment of the present invention, the logic transistor is located in a first region of the semiconductor device and the fieldless array transistors are located in a second region of the semiconductor device. A polysilicon layer is formed over the first and second regions of the semiconductor device. The polysilicon layer over the first region of the semiconductor device is etched to define the gates of the logic transistors. However, at this point the polysilicon layer over the second region of the semiconductor device is not etched. Ion implantation over the surface of the semiconductor device creates self-aligned low doped source and drain regions for the logic transistor. Oxide spacers are then formed for the logic transistors. When the oxide spacers are formed in the first region, the entire second region remains covered with polysilicon, thereby preventing undesirable etching in the fieldless array. An implant process implants ions for the highly doped source and drain active regions of the logic transistor. The semiconductor device is then annealed to create the source and drain regions of the logic transistor. An oxide etch is used to remove any oxide on the source and drain regions created during the annealing of the semiconductor device. A refractory metal layer is subsequently deposited over the upper surface of the semiconductor device. The semiconductor device is annealed to cause the portions of the refractory metal layer to react with any silicon in contact with the refractory metal layer to form silicide. At this time, silicide is formed over the source and drain active regions of the logic transistor, the polysilicon gate of the logic transistor, and the polysilicon layer overlying the entire second region. The portions of the refractory metal layer not in contact with silicon are removed using a refractory metal etching process. The polysilicon and silicide overlying the second region of the semiconductor devices are then etched to form the gates of the fieldless array transistors.
The above-described process steps advantageously enable CMOS transistors having self aligned silicide gates structures and fieldless array transistors to be fabricated on the same wafer in an efficient manner. The present invention will be more fully understood in view of the following description and drawings.
REFERENCES:
patent: 5219775 (1993-06-01), Saeki et al.
patent: 5610420 (1997-03-01), Kuroda et al.
patent: 5768192 (1998-06-01), Eitan
patent: 5966603 (1999-10-01), Eitan
Bever Hoffman & Harms LLP
Loke Steven H.
Mao Edward S.
Parekh Nitin
Tower Semiconductor Ltd.
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