Semiconductor chip having bond pads and multi-chip package

Details Semiconductor chip having bond pads and multi-chip package Semiconductor chip having bond pads and multi-chip package

2002-07-09

2003-11-04

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

C257S301000, C257S302000, C257S754000, C257S760000, C257S315000

Reexamination Certificate

active

06642627

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices and, more particularly, to a semiconductor chip having bond pads and to a multi-chip package (MCP).
2. Description of the Related Art
The industry is expending significant effort toward forming smaller and thinner chips to meet the demand for high packing density in high-speed, multi-functional semiconductor devices. To reduce chip size, the size of bond pads as well as the pitch between bond pads should be reduced.
Conventional semiconductor chips have either a center pad-type or a peripheral pad-type structure.
FIG. 1
is a plan view of a conventional center pad-type semiconductor chip.
FIG. 2
is a cross-sectional view of the conventional center pad-type chip taken along line
2
—
2
of FIG.
1
.
FIG. 3
is a plan view of a conventional peripheral pad-type semiconductor chip.
FIG. 4
is a cross-sectional view of the conventional peripheral pad-type chip taken along the line
4
—
4
of FIG.
3
.
Referring to
FIGS. 1 and 2
, a center pad-type semiconductor chip
110
comprises a peripheral circuit region A
peri
for forming bond pads
112
and cell regions A
cell1
and A
cell2
. The peripheral circuit region A
peri
is formed in the center region of a semiconductor substrate
111
. The cell regions A
cell1
and A
cell2
are formed on the sides of the peripheral circuit region A
peri
.
Referring to
FIGS. 3 and 4
, a peripheral pad-type semiconductor chip
120
comprises peripheral circuit regions A
peri1
and A
peri2
, and a cell region A
cell
. The cell region A
cell
is formed in the center region of the semiconductor substrate
121
. The peripheral circuit regions A
peri1
and A
peri2
are formed on the sides of the cell region A
cell
. Referring to
FIGS. 2 and 4
, a passivation layer
113
,
123
is formed over the cell regions and the peripheral circuit regions in both the center and peripheral pad-type chips.
In the conventional semiconductor chips
110
,
120
of
FIGS. 1 through 4
, an additional chip area is needed in peripheral circuit regions for forming bond pads
112
,
122
. As a result, the ability to reduce the size of the conventional semiconductor chips
110
and
120
is limited in both chip pad types.
Furthermore, it has been difficult to reduce the bond pad size and the pitch between the bond pads
112
,
122
in the conventional semiconductor chips
110
and
120
. This is because the bond pads
112
,
122
must have a designed minimum size and pitch for electric die sorting (EDS) and to form electrical interconnections.
The ability to reduce the size of a multi-chip package (MCP) including multiple conventional semiconductor chips in a single body package is also limited due to problems such as the difficulty of stacking center pad-type chips on chips of the same or similar types. That is, wire bonding can be complicated and difficult due to long loop wires in such cases.
Accordingly, there is a need for a smaller semiconductor chip that can easily form an MCP without suffering from the problems mentioned above.
SUMMARY OF THE INVENTION
A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. According to one embodiment, the bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. According to another embodiment, a portion of the pad-rearrangement pattern extends substantially from the center region of the semiconductor substrate toward an edge of the semiconductor substrate. According to yet another embodiment, the bond pad-wiring pattern is form on a portion of the peripheral circuit region and extends across a portion of the cell region.
Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above, thus reducing manufacturing costs and increasing productivity.


REFERENCES:
patent: 4984050 (1991-01-01), Kobayashi
patent: 5723822 (1998-03-01), Lien
patent: 5751065 (1998-05-01), Chittipeddi et al.
patent: 6111317 (2000-08-01), Okada et al.
patent: 06-275794 (1994-09-01), None
patent: 08-340002 (1996-12-01), None
patent: 09-107048 (1997-04-01), None
patent: 11-111896 (1999-04-01), None
patent: 11-040624 (1999-12-01), None
patent: 2000-031191 (2000-01-01), None
patent: 2000-183090 (2000-06-01), None
patent: 2000-294519 (2000-10-01), None
English language abstract of Japanese Patent No. 06275794.
English language abstract for Japan Patent Publication No. 08-340002.
English language abstract for Japanese Patent Publication No. 09-107048.
English language abstract for Japanese Patent Publication No. 11-040624.
English language abstract for Japanese Patent Publication No. 11-111896.
English language abstract for Japanese Patent Publication No. 2000-031191.
English language abstract for Japanese Patent Publication No. 2000-183090.
English language abstract for Japanese Patent Publication No. 2000-294519.

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