Semiconductor associative memory device with address corrector f

Static information storage and retrieval – Read/write circuit – Bad bit

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36518907, G11C 2900

Patent

active

056778830

ABSTRACT:
A semiconductor associative memory device directly supplies status signals each representative of matching state or mismatching state from regular/redundant memory words to an address generator for generating a preliminary address signal representative of the regular/redundant memory word supplying the status signal representative of the matching state, and an address correcting system examines the preliminary address signal to see whether or not the preliminary address signal is representative of one of the regular/redundant memory word affected by a replacement of a defective regular memory word with the redundant memory word; when the preliminary address signal is representative of the regular/redundant memory word, the address correcting system generates a formal address signal representative of the address of one of the regular memory words expected to store the data code matched with a given data code if all the regular memory words are excellent at storing data codes.

REFERENCES:
patent: 5319589 (1994-06-01), Yamagata
patent: 5528540 (1996-06-01), Shibata

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