Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1997-12-04
2000-03-28
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438301, 438357, 438591, 438592, H01L 213205, H01L 214763
Patent
active
060431423
ABSTRACT:
In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.
REFERENCES:
patent: 4249968 (1981-02-01), Gardiner et al.
patent: 4319954 (1982-03-01), White et al.
patent: 4354309 (1982-10-01), Gardiner et al.
patent: 4358326 (1982-11-01), Doo
patent: 4415383 (1983-11-01), Naem et al.
patent: 4742020 (1988-05-01), Roy
patent: 4777150 (1988-10-01), Deneuville et al.
patent: 4810637 (1989-03-01), Szydlo et al.
patent: 4870031 (1989-09-01), Sugahara et al.
patent: 4873204 (1989-10-01), Wong et al.
patent: 4897150 (1990-01-01), Dooley et al.
patent: 4971919 (1990-11-01), Yamazaki
patent: 4985371 (1991-01-01), Rana et al.
patent: 5037774 (1991-08-01), Yamawaki et al.
patent: 5147820 (1992-09-01), Chittepeddi et al.
patent: 5155051 (1992-10-01), Noguchi et al.
patent: 5177569 (1993-01-01), Koyama et al.
patent: 5256894 (1993-10-01), Shino
patent: 5298436 (1994-03-01), Radosevich et al.
patent: 5306651 (1994-04-01), Masumo et al.
patent: 5381032 (1995-01-01), Kokawa et al.
patent: 5481128 (1996-01-01), Hong
patent: 5720074 (1998-02-01), Ohshimo
Wu et al, "High-Performance Polysilicon Contacted Shallow Junctions Formed by Stacked-Amorphous-Silicon Films," IEEE Electron Device Letters, vol. 13, No. 1, pp. 23-25, Jan. 1992.
Miura Hideo
Nakajima Takashi
Ohta Hiroyuki
Okamoto Noriaki
Hack Jonathan
Hitachi , Ltd.
Niebling John F.
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