Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-05-10
2011-05-10
Fulk, Steven J (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S370000, C257SE29293
Reexamination Certificate
active
07939402
ABSTRACT:
A method for manufacturing a semiconductor apparatus is disclosed. The apparatus comprises double poly bipolar transistors and double poly metal oxide semiconductor (MOS) transistors. The bipolar transistors and the MOS transistors are manufactured in a unified process in which a first polysilicon layer (Poly1) is doped to form the extrinsic bases in the bipolar transistors and to form the gates in the MOS transistors. A second polysilicon layer (Poly2) is doped to form emitters in the bipolar transistors and to form the sources and drains in the MOS transistors. The method of the invention minimizes the number of manufacturing process steps.
REFERENCES:
patent: 4318751 (1982-03-01), Horng
patent: 4475279 (1984-10-01), Gahle
patent: 4545087 (1985-10-01), Nahum
patent: 4735916 (1988-04-01), Homma et al.
patent: 4784971 (1988-11-01), Chiu et al.
patent: 4887142 (1989-12-01), Bertotti et al.
patent: 4902640 (1990-02-01), Sachitano et al.
patent: 4922318 (1990-05-01), Thomas et al.
patent: 4960726 (1990-10-01), Lechaton et al.
patent: 5011784 (1991-04-01), Ratnakumar
patent: 5017995 (1991-05-01), Soejima
patent: 5028557 (1991-07-01), Tsai et al.
patent: 5037768 (1991-08-01), Cosentino
patent: 5091760 (1992-02-01), Maeda et al.
patent: 5104816 (1992-04-01), Verret et al.
patent: 5108945 (1992-04-01), Matthews
patent: 5141891 (1992-08-01), Arima et al.
patent: 5294558 (1994-03-01), Subbanna
patent: 5340751 (1994-08-01), Maeda et al.
patent: 5943564 (1999-08-01), Chen et al.
patent: 6441441 (2002-08-01), Suda
patent: 6472324 (2002-10-01), Kusakabe et al.
patent: 2001/0005608 (2001-06-01), Johansson et al.
S. Hsia et al., “Polysilicon Oxidation Self-Aligned MOS (POSA MOS)—A New Self-Aligned Double Source/Drain Ion Implantation Technique for VLSI”, IEEE Electron Device Letters, vol. EDL-3, No. 2, Feb. 1982, pp. 40-42.
Kamal Rajkanan et al., “A High-Performance BICMOS Technology with Double-Polysilicon Self-Aligned Bipolar Devices”, IEEE Electron Device Letters, vol. EDL-8, No. 11, Nov. 1987, pp. 509-511.
Tiao-Yuan Huang et al., “A MOS Transistor with Self-Aligned Polysilicon Source-Drain”, IEEE Electron Device Letters, vol. EDL-7, No. 5, May 1986, pp. 314-316.
C. S. Oh et al., “A New MOSFET Structure with Self-Aligned Polysilicon Source and Drain Electrodes”, IEEE Electron Device Letters, vol. EDL-5, No. 10, Oct. 1984, pp. 400-402.
W. Josquin et al., “The Integration of Double-Polysilicon NPN Transistors in an Analog BiCMOS Process”, Extended Abstracts of the 20th (1988 International) Conference on Solid State Devices and Materials, Tokyo, 1988 pp. 149-152.
Kwang Soo Kim et al., Bipolar-Complementary-Metal-Oxide-Semiconductor (BiCMOS) Technology with Polysilicon Self-Aligned Bipolar Devices, Japanese Journal of Applied Physics, vol. 30, No. 10, Oct. 1991, pp. 2459-2465.
Masahiro Shimizu et al., “A Novel CMOS Structure with Polysilicon Source/Drain (PSD) Transistors by Self-Aligned Silicidation”, IEICE Trans. Electron, vol. E76-C, No. 4, Apr. 1993, pp. 532-540.
M. K. Moravvej-Farshi et al., Novel Self-Aligned Polysilicon-Gate MOSFETS with Polysilicon Source and Drain, Solid-State Electronics, vol. 30, No. 10, 1987, pp. 1053-1062.
W. R. Burger et al., “An Advanced Self-Aligned BiCMOS Technology for High Performance 1-MegaBit ECL I/O SRAM's”, National Semiconductor Corp., Puyallup Technology Development, 1989.
James Warnock et al., “BiCMOS Technology with 60-Ghz n-p-n. Bipolar and 0.25-1μm CMOS”, IEEE Electron Device Letters, vol. 13, No. 11, Nov. 1992, pp. 578-580.
J. D. Hayden et al., “Integration of a Double Polysilicon, Fully Self-Aligned Bipolar Transistor into a 0.5μm BiCMOS Technology for Fast 4MBit SRAMs”, Advanced Products Research and Development Laboratory, Motorola Inc., IEEE 1991 Bipolar Circuits and Technology Meeting, pp. 17-20.
T. C. Mele et al., “A High Performance 0.5μm BiCMOS Triple Polysilicon Technology for 4mb Fast SRAMs”, Advanced Products Research and Development Laboratory, Motorola Inc., IEEE 1990.
Kenneth O'Peter Garone et al., “A Double-Polysilicon Self-Aligned npn Bipolar Process (ADRF) with Optional NMOS Transistors for RF and Microwave Applications”, 1994 Bipolar/BiCMOS Circuits & Technology Meeting, pp. 221-224.
Alain Chantre et al., “Identification of a Corner Tunneling Current Component in Advanced CMOS-Compatible Bipolar Transistors”, IEEE Transactions on Electron Devices, vol. 38, No. 1, Jan. 1991, pp. 107-110.
K. Ishimaru et al., “Bipolar Installed CMOS Technology without Any Process Step Increase for High Speed Cache SRAM”, IEEE 1995.
Tzu-Yin Chin et al., “The Design and Characterization of Nonoverlapping Super Self-Aligned BiCMOS Technology”, IEEE Transactions on Electron Devices, vol. 38, No. 1, Jan. 1991, pp. 141-150.
Tadanori Yamaguchi et al., “Process Integration and Device Performance of a Submicrometer BiCMOS with 16-Ghz ft Double Poly-Bipolar Devices”, IEEE Transactions on Electron Devices, vol. 36, No. 5, May 1989, pp. 890-896.
T. Yuzuriha et al., “Submicron Bipolar-CMOS Technology Using 16 Ghz ft Double Poly-SI Bipolar Devices”, Tektronix, Inc. IEEE 1988, pp. 748-751.
T. Yoshimura et al., “0.6 μm High Speed BiCMOS Technology with Emitter-Base Self-Aligned Structure”, Fujitsu Limited, Bipolar IC Division, IEEE 1989, pp. 241-244.
K. G. Moerschel et al., “Best: A BiCMOS-Compatible Super-Self-Aligned ECL Technology”, AT&T Microelectronics, AT&T Bell Laboratories, IEEE 1990 Custom Integrated Circuits Conference, pp. 18.3.1-18.3.4.
S. Wolf, “Silicon Processing for the VLSI Era: The Submicron MOSFET”, 1995, vol. 3, pp. 641-642.
M. Shimizu et al., “A Novel Polysilicon Source/Drain Transistor with Self-Aligned Silicidation”, LSI R&D Laboratory, Mitsubishi Electric Corporation, pp. 11-12, (No Date).
Tunenori Yamauchi et al., “High Speed BICMOS Technology with Emitter-base Self-aligned Structure”, Bipolar IC Division Fujitsu Limited, pp. 155-158, (No Date).
Shih Wei Sun et al., “Selective-Polysilicon Emitter, Self-Aligned Bipolar Structure for BiCMOS VLSI Applications”, Motorola Inc., Advanced Products Research and Development Laboratory, pp. 55-56, (No Date).
Foote Richard W.
Oliver Robert
Fulk Steven J
National Semiconductor Corporation
LandOfFree
Semiconductor apparatus comprising bipolar transistors and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor apparatus comprising bipolar transistors and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor apparatus comprising bipolar transistors and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2686819