Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
2002-01-24
2003-03-25
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S781000
Reexamination Certificate
active
06538335
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor apparatus and a semiconductor device mounting method. More particularly, the present invention relates to a semiconductor apparatus and a semiconductor device mounting method in which a mechanical connection force is improved between a substrate and a semiconductor device.
2. Description of the Related Art
In recent years, the miniaturization of an electronic apparatus has been advanced, and its price has come down. In association with them, a flip-chip method is proposed as a structure in which semiconductor devices are mounted at a high density.
The semiconductor device mounting method in the flip-chip method is the method of connecting a semiconductor device, in which a plurality of bump electrodes are mounted on at least one surface, to a circuit substrate, by performing a face-down on a side on which the bump is mounted.
A conventional flip-chip mounting structure will be described below with reference to FIG.
1
.
As shown in
FIG. 1
, in the conventional flip-chip mounting structure, a mount pad
73
is formed on a circuit substrate
71
. A plurality of bumps
74
is formed on the surface of the side of the circuit substrate
71
on a semiconductor device
72
. The mount pad
73
is usually produced by copper plating. Nickel-gold plating is coated thereon. Its surface is relatively smooth.
Then, the semiconductor device
72
is mounted on the substrate
71
by connecting the mount pad
73
to the bump
74
. The followings are the conventional connecting methods.
As a first method, a gold protruded bump (bump
74
) is firstly formed on the semiconductor device
72
by using a wire bonding method. Next, Ag paste is coated on an upper portion of the protruded bump. Then, the protruded bump is pushed against the mount pad
73
, and adhered thereto (Journal of Japan Institute for Interconnecting and Packaging Electronic Circuits, Vol. 11, No.5 (1996) P347).
As a second method, the gold protruded bump (bump
74
) is firstly formed on the semiconductor device
72
by using the wire bonding method. Then, the protruded bump and the substrate
71
are soldered to each other (Journal of Japan Institute for Interconnecting and Packaging Electronic Circuits, Vol. 11, No.5 (1996) P319).
And, as a third method, the gold protruded bump (bump
74
) is firstly formed on the semiconductor device
72
by using the wire bonding method. Next, solder is sent to the mount pad
73
. Then, the bump
74
and the mount pad
73
are soldered to each other (Journal of Japan Institute for Interconnecting and Packaging Electronic Circuits, Vol. 11, No.5 (1996) P343).
In all the above-mentioned methods, as shown in
FIG. 1
, after the semiconductor device
72
is placed on the substrate
71
, a seal resin
75
is filled between them. In this configuration, the pad
73
and the bump
74
are integrally bonded over the boundary between them. However, the thermal expansion coefficient of the semiconductor device
72
is different from that of the substrate
71
. In particular, it differs from an organic substrate by as much as five times. For this reason, large stress is induced in a connection portion, which may result in an occurrence of a connection defect. Thus, by filling the seal resin
75
between the semiconductor device
72
and the substrate
71
, it is necessary to disperse the stress.
A connecting method of using a contraction force of the seal resin
75
will be described below with reference to
FIGS. 2A
to
2
B. At first, the seal resin
75
is placed on the substrate
71
on which the semiconductor device
72
is placed. Next, as shown in
FIG. 2B
, a position of the semiconductor device
72
is made coincident with that of the mount pad
73
by carrying out the face-down. As shown in
FIG. 2C
, while the semiconductor device
72
is placed on the substrate
71
and a tip of the bump
74
is deformed under a heating and pressing process, the mount pad
73
and the bump
74
come in direct contact with each other. At that time, until the seal resin
75
is cured, the heating and pressing process is continued to thereby obtain the mechanical electronic connection.
In the above-mentioned methods, the semiconductor device
72
and the substrate
71
are not mechanically fixed until the seal resin
75
is cured. For this reason, it is difficult that immediately after placing the semiconductor device
72
on the substrate
71
, it is moved to another apparatus and the heating and pressing process is done in order to shorten an occupation time of the mounted unit.
In view of the above-mentioned circumstances, a semiconductor apparatus having an excellent productivity is desirable in which the mechanical connection force is improved between the substrate
71
and the semiconductor device
72
.
As the related technique, Japanese Laid Open Patent Application (JP-A-Heisei 10-50765) discloses a method of mounting a semiconductor device and a technique of a semiconductor apparatus. The semiconductor apparatus based on this technique is formed by mounting the semiconductor device on a substrate. It has a mount pad, a bump electrode and a seal resin. Here, the mount pad is formed on the substrate, and it has a concave and convex portion on the surface thereof. The bump electrode is formed on the surface of the substrate side of the semiconductor device, and it is arranged while it is inserted into the concave and convex portion of the mount pad. The seal resin exists between the semiconductor device and the substrate.
It is described that this technique is used to insert the bump electrode into the concave and convex portion formed on the surface of the mount pad, and the connection strength is improved.
Japanese Laid Open Patent Application (JP-A-Heisei 7-201917) discloses a technique of a circuit formation substrate and a method of manufacturing the same. The circuit formation substrate based on this technique has an electrically insulating substrate, a thin film metallic electrode disposed on a surface of the electrically insulating substrate, and an electronic part electrically connected through a bump to the thin film metallic electrode. Then, a concave and convex layer is formed on the surface of the thin film metallic electrode or the electrically insulating substrate of the ground thereof.
It is described that since the respective bonding conditions (contacts) between the electrically insulating substrate, the thin film metallic electrode and the bump can be made stronger by using this technique, the reliability can be improved.
Japanese Laid Open Patent Application (JP-A-Heisei 10-270498) discloses a technique of a method of manufacturing an electronic apparatus. The electronic apparatus manufacturing method based on this technique includes the steps of: preparing an electronic device in which a solder protrusion electrode is formed on a surface; preparing a wiring substrate in which a needle-like electrode made of a material having a melting point higher than that of a member of the solder protrusion electrode and having a high elastic coefficient is formed on a surface; making a position of the solder protrusion electrode and a position of the needle-like electrode coincide with each other, pushing the needle-like electrode until it reaches a ground electrode of the solder protrusion electrode and carrying out a tentative connection; and performing a re-flow on the solder protrusion electrode and regularly connecting the electronic device and the wiring substrate to each other.
It is described that this technique can shorten the step of manufacturing the electronic apparatus and can also improve the yield of the electronic apparatus.
However, since the semiconductor apparatuses disclosed in the above-mentioned gazette have the concave and convex portion on the surface of the substrate, they are strong against a stress in a flat direction, and weak against a vertical force. This is because their convex portion and needle-like electrode are wide near the side of the surface of the mount pad,
Ohuchi Rieka
Shimada Toshiyasu
Choate Hall & Stewart
Clark Sheila V.
NEC Corporation
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