Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
1998-04-23
2001-02-20
Whitehead, Jr., Carl (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S737000
Reexamination Certificate
active
06191487
ABSTRACT:
BACKGROUND OF THE INVENTION
The semiconductor industry has continued to provide products with increased speed and memory while at the same time reducing the overall space requirements of the integrated circuits and electronics associated with these improved products. However, pressure still exists within the industry to reduce the size of circuits and space requirements of the electrical components on the printed circuit boards so that the overall size of the electronic device (such as a cellular telephone) is minimized. The industry has developed a “chip-scale” standard to define minimum space requirements for semiconductor components. A chip-scale circuit is one that has an area equal to or less than 1.2 times the area of the die used to make the device.
Semiconductor chip manufacturers have typically focused on reductions in size of memory modules and microprocessors. For example, large scale integrated circuits, such as microprocessors are typically tab-leaded, flip chip bumped or coated onto the printed circuit board. However, the smaller pin count components such as transistors, diodes and FETs are still connected using lead frame technology to the printed circuit board. The reduction in size of these smaller pin count semiconductor chips to chip-scale dimensions or near chip scale dimensions would further decrease the overall size of semiconductor circuit boards.
Various methods have been used to accomplish reductions in size, including “flip-chip” technologies. In a flip chip devise, the flip chip bonding is a technique of using solder balls to solder the chips face down on a substrate. An example of flip chip bump bonding is shown in U.S. Pat. No. 4,912,545.
A conductive epoxy has also been used to making a frontside connection from multiple die to a substrate. An example of this can be seen in U.S. Pat. No. 5,657,206 where the connection is made from the die front Oside to the substrate.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor chip package with a back side connection and method of manufacture that substantially eliminates or reduces disadvantages and problems associated with previously developed semiconductor chip packages and methods of manufacture.
More specifically, the present invention provides a semiconductor chip package having a back side connection. The semiconductor chip package includes a die with bond pads to connect to a substrate. The substrate includes terminals opposite the side facing the die that electrically connect to contact pads on the opposite side of the substrate by way of vias that electrically connect the contact pads to the terminals. In one embodiment, the vias can be buried in the substrate. The back side of the die is electrically connected to a bond pad (and thereby to the terminal through the via) using a conductive substance that can cascade from the back side of the die to the bond pad. Solder balls can be attached to the terminals to provide solder connections to a printed circuit board. An insulating coating can be applied to the die between the conductive substance and the edge of the die along which the conductive substance cascades.
In an alternative embodiment, the substrate is eliminated and the conductive substance will make a connection from the die back side directly to the printed circuit board at an etch or pad.
The present invention provides a technical advantage by reducing the area required for discreet devises and integrated circuits formed from standard die having back side connections. The present invention eliminates the requirement for lead wires extending from the die in a flip chip package to the printed circuit board, thereby reducing the space required to connect the flip chip device to the remainder of the circuit.
The present invention provides another technical advantage by allowing the use of standard back side connection die. The present invention can use the existing bond pads and industry standard die without modification of the die.
REFERENCES:
patent: 4912545 (1990-03-01), Go
patent: 5394303 (1995-02-01), Yamaji
patent: 5406701 (1995-04-01), Pepe et al.
patent: 5432729 (1995-07-01), Carson et al.
patent: 5569880 (1996-10-01), Galvagni et al.
patent: 5657206 (1997-08-01), Pedersen et al.
patent: 5737191 (1998-04-01), Horiuchi et al.
patent: 5869886 (1999-02-01), Tokuno
Potter Donald R.
Rodenbeck Lloyd R.
Gray Cary Ware and Freidenrich
Jr. Carl Whitehead
Minco Technology Labs, Inc.
Potter Roy
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