Semiconductive memory device with current control and comparison

Details Semiconductive memory device with current control and comparison Semiconductive memory device with current control and comparison

1987-03-17

1989-01-24

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365104, 365105, 365208, G11C 700

Patent

active

048005290

ABSTRACT:
A memory device comprises an access circuit for setting a selected one of word lines to a low (or high) level responsive to a row address and for setting a selected one of bit lines to a high (or low) level responsive to a columnm address so as to designate a memory cell within a memory cell array, a comparing circuit driven by a constant current source for reading out information from the designated memory cell via the bit lines by comparing the bit line level with a reference level, an output circuit for outputting the information read out by the comparing circuit, and a control circuit for either setting all of the word lines and bit lines to a high level or setting all of the word lines and bit lines to have a high impedance and setting the impedance at an output of the output circuit to a high impedance when the memory device is disabled, so as to reduce the power consumption when the memory device is disabled.

REFERENCES:
patent: 4162540 (1979-07-01), Ando
patent: 4171538 (1979-10-01), Sheller
patent: 4195358 (1980-03-01), Yuen
patent: 4319341 (1982-03-01), Fukushima et al.
patent: 4441167 (1984-04-01), Principi
patent: 4672576 (1987-06-01), Davis
patent: 4713797 (1987-12-01), Morton et al.

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