Semi-shared sense amplifier and global read line architecture

Details Semi-shared sense amplifier and global read line architecture Semi-shared sense amplifier and global read line architecture

2007-03-30

2010-02-02

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S205000

Reexamination Certificate

active

07656731

ABSTRACT:
A memory includes a global read line and a plurality of banks. For each bank, the memory includes a sense amplifier. A discharge circuit discharges the global read line if any one of a plurality of the sense amplifiers is enabled and is outputting a signal having a first digital logic value onto an input lead of the discharge circuit. In this way, the sense amplifiers share the discharge circuit. In one example, the memory includes a pair of differential read lines that are precharged to begin a read operation. After precharging, if either of two sense amplifiers is enabled and outputting the first digital logic value, then a first discharge circuit discharges a first of the global read lines. If either of two sense amplifiers is enabled and outputting the second digital logic value, then a second discharge circuit discharges a second of the global read lines.

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International Search Report-PCT/US2008/057430, International Searching Authority-European Patent Office-Sep. 18, 2008.
Written Opinion-PCT/US2008/057430, International Searching Authority-European Patent Office-Sep. 18, 2008.

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