Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-07-07
2002-09-03
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06444516
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to transmission lines for microcircuits. More particularly, this invention relates to a diffusion barrier for low-resistance gate conductors for metal-oxide-semiconductor field-effect transistors (MOSFETs), in which the diffusion barrier is formed of a semi-insulating material that is able to prevent degradation of a gate conductor at high processing temperatures encountered during the fabrication of MOSFET and CMOS devices.
2. Description of the Prior Art
As known in the art, the gate of a field effect transistor (FET) typically includes a gate insulator over a semiconductor substrate, over which a polysilicon gate electrode is formed to which a voltage is applied to invert the surface of the substrate beneath the electrode, forming a channel through which electrons or holes flow from the source toward the drain of the transistor. The gate structure further includes a gate conductor that is electrically connected with the gate electrode, and by which the gate signal is delivered to the gate electrode. In addition to having low electrical resistance to minimize gate signal delay, the gate conductor of a MOSFET is often required to withstand high processing temperatures, for example, above 1050° C. for junction activation. This process integration constraint has necessitated a tradeoff between the conductivity and thermal stability of the gate conductor material. Gate conductors formed of tungsten or titanium suicides (TiSi
x
) have low resistivities, on the order of about 15 to 20 micro-ohms·cm, but cannot withstand junction activation without degradation from interdiffusion with the polysilicon gate electrode, leading to a sharp increase in resistivity and/or causing a depletion of dopant from the gate electrode. Furthermore, TiSi
x
tends to agglomerate at temperatures above about 900° C., and pure tungsten reacts with polysilicon at temperatures above about 750° C. to form tungsten silicides (WSi
x
), which exhibit high resistivities on the order of about 200 micro-ohms·cm, and therefore undesirably increase gate propagation delay. Even so, tungsten silicides are more thermally stable as compared to tungsten metal and titanium silicides, and are therefore employed as the material for gate conductors if processing temperatures will exceed the capability of tungsten and titanium silicide.
One known approach to prevent degradation of a gate structure having a tungsten gate conductor is to provide a diffusion barrier between the conductor and polysilicon electrode. In order to avoid undue delay in the gate signal, more current leakage through the diffusion barrier is better. Consequently, conventional wisdom has been to use conductive materials, such as TiN, TaSiN or tungsten nitride (WN
x
) as the diffusion barrier material. However, conductive diffusion barrier materials such as TiN and TaSiN are limited to processing temperatures of less than about 900° C. in order to prevent breakdown of the material (TiN and WN
x
) or prevent thermal oxidation of the material (TiN or TaSiN). Accordingly, conductive diffusion barrier materials currently available cannot withstand temperatures sufficient for junction activation and other high-temperature processes necessary in the fabrication of MOSFETs, or are otherwise not sufficiently oxidation resistant or compatible with integrated circuit manufacturing to successfully serve as a diffusion barrier for a gate electrode.
In view of the above, what is needed is a gate structure that is capable of withstanding processing temperatures above 900° C., and preferably at least 1050° C. for junction activation, without significantly increasing gate propagation delay.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a gate structure for a semiconductor device, and particularly a MOSFET for such applications as CMOS technology. The gate structure of this invention can employ a gate conductor that has relatively low resistivity, e.g., tungsten or titanium silicide, yet remains thermally stable at processing temperatures above 900° C. As a result, the gate structure can exhibit low gate propagation delay while also being capable of withstanding high temperature processes such as junction activation.
As with conventional processes, the gate structure of this invention generally entails an electrical insulating layer on a semiconductor substrate, over which a polysilicon gate electrode is formed. The gate structure further includes a gate conductor that is electrically connected with the electrode via a diffusion barrier, which separates the gate electrode and gate conductor to prevent interdiffusion therebetween. Because the gate electrode voltage controls the speed of the transistor, the voltage drop across the diffusion barrier must be minimal in order to achieve a maximum switching speed for the transistor at a given swing of the gate voltage. For this reason, only highly conductive materials have been considered in the past as potential candidates for diffusion barrier of gate structures. Conductive materials such as metals and certain semimetals, metal silicides, metal nitrides, and doped semiconductors generally have resistivities in the range of about 10
−6
to 10
−2
ohms-cm. On the other hand, typical insulator materials have resistivities in the range of about 10
6
to 10
18
ohms-cm. A material having a resistivity between 10
−2
and 10
6
ohms-cm (i.e., between that of “good” conductor materials and “good” insulator materials) may be referred to as either an imperfect insulator or a poor conductor, depending of whether its resistivity is closer to that of an insulator or conductor material.
Contrary to conventional wisdom, the diffusion barrier of this invention is a very thin layer of a material with semi-insulating properties, which are defined by the ability of the diffusion barrier to allow for a flow of the leakage current (expressed in Amps per unit of area at a specified voltage). According to the invention, transistor speed is not significantly affected if the diffusion barrier provides sufficient capacitive coupling between the gate conductor and electrode, and/or allows sufficient leakage current from the gate conductor to the electrode. For example, a sufficient leakage current through a diffusion barrier is in the range of about 10
−8
to 1 A/&mgr;m
2
based on one Volt bias across the barrier. Both leakage current and the degree of gate electrode charging due to capacitive coupling is increased as the thickness of the diffusion barrier is reduced.
In general, the leakage current may not be a linear function of the voltage across the diffusion barrier, such that barrier resistance and resistivity may depend on the voltage. Nevertheless, a comparison of the resistance, resistivity, and leakage current of semi-insulating materials at a specified voltage has demonstrated that very thin (e.g., about 0.5 to about 10 nm) semi-insulating (bulk resistivity of between 10
−2
and 10
6
ohms-cm) diffusion barriers have leakage currents within the above-noted desired range of 10
−8
to 1 A/&mgr;m
2
at 1 Volt bias. In contrast, based on a typical contact resistance (resistance of unit contact area) of less than 10
−8
ohm-cm
2
, conventional conductive diffusion barriers have a leakage current of more than 1 A/&mgr;m
2
at 1 Volt bias. The same is true even for very thin (e.g., about 0.5 to about 10 nm) conductive diffusion barriers. Accordingly, the semi-insulating diffusion barriers of this invention are also distinguishable from conventional conductive diffusion barriers by having lower leakage currents.
The semi-insulating quality of the diffusion barrier of this invention can be achieved by employing one of several techniques or their combinations. In one approach, the thickness of a diffusion barrier formed of a good bulk insulator is optimized to allow for a sufficient tunneling current while preventing diffusion and intermixing of gate conductor and electrode materials during high-tem
Clevenger Lawrence Alfred
Faltermeier Johnathan
Gluschenkov Oleg
Jammy Rajarao
Mandelman Jack A.
August Casey P.
Hartman Domenica N. S.
Hartman Gary M.
Stevenson André C
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