Semi-flattened pin optimization process for hierarchical...

Details Semi-flattened pin optimization process for hierarchical... Semi-flattened pin optimization process for hierarchical...

2006-09-13

2008-12-23

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S013000, C703S014000

Reexamination Certificate

active

07469399

ABSTRACT:
In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access.

REFERENCES:
patent: 6345381 (2002-02-01), Leight et al.
patent: 6357035 (2002-03-01), Gowni et al.
patent: 6415428 (2002-07-01), Camporese et al.
patent: 6662349 (2003-12-01), Morgan et al.
patent: 6883156 (2005-04-01), Khainson et al.
patent: 2002/0261048 (2004-12-01), Bucki et al.
patent: 2001-53154 (2001-02-01), None

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