Self-verification of configuration memory in programmable...

Details Self-verification of configuration memory in programmable... Self-verification of configuration memory in programmable...

2008-07-15

2008-07-15

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S736000

Reexamination Certificate

active

11750790

ABSTRACT:
In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit; an error detection circuit operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the error detection circuit calculating a signature that includes configuration bits and masking values; and a comparator operable to compare the signature calculated by the error detection circuit with a correct signature.

REFERENCES:
patent: 4441074 (1984-04-01), Bockett-Pugh et al.
patent: 6158033 (2000-12-01), Wagner et al.
patent: 2005/0071730 (2005-03-01), Moyer et al.

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