Self-timed programmable logic array with pre-charge circuit

Details Self-timed programmable logic array with pre-charge circuit Self-timed programmable logic array with pre-charge circuit

1988-12-22

1990-04-03

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

365206, G11C 1300

Patent

active

049146335

ABSTRACT:
A programmable logic array includes a decoder section and an encoder section connected by a plurality of minterm conductors. The decoder section receives a plurality of input signals and in response selects appropriate ones of the minterm conductors. The selection of the minterm conductors enable the encoder selection to transmit a plurality of output signal on respective output conductors. The decoder and encoder sections include a plurality of stages, each controlling a minterm conductor and output conductor in response to the input signals and the selection of the minterm conductor. The stages include control transistors that are connected between a node, to which the respective minterm and output conductors are connected, and switches which enable and disable the control transistors. The nodes are initially precharged while the switches disable the respective transistors. After precharge, the switches enable the transistors in the decoder and encoder section respectively. A self timing circuit controls the switches to ensure that the switches are correctly timed.

REFERENCES:
patent: 4644500 (1987-02-01), Yonezu et al.
patent: 4794570 (1988-12-01), Rose et al.
IEEE Journal of Solid-State Circuits, vol. SC-16, No. 2, Apr. 1981, pp. 103-107, New York, U.S.; C. M. Lin: "A 4 mum NMOS and Structure PLA".

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