Self-timed precharge circuit

Details Self-timed precharge circuit Self-timed precharge circuit

1985-01-31

1987-01-20

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Precharge

365230, 365227, G11C 700

Patent

active

046384626

ABSTRACT:
A self-timed precharge circuit for a memory array consisting of an X-line complement circuit connected to the outputs of a plurality of falling edge detectors, and a precharge generator circuit connected to the output of the X-line complement circuit. Each falling edge detector is connected to a separate wordline (WL, WL+1, . . . WL+N) of the system memory array. In operation, the precharge generator circuit is triggered with a signal on the output lead from a falling edge detector which is activated when the selected wordline (WL, WL+1, . . . WL+N) connected thereto resets.

REFERENCES:
patent: 3909631 (1975-09-01), Kitagawa
patent: 3942037 (1976-03-01), Mensch, Jr.
patent: 3942162 (1976-03-01), Buchanan
patent: 4110840 (1978-08-01), Abe et al.
patent: 4208730 (1980-06-01), Dingwall et al.
patent: 4322825 (1982-03-01), Nagami
patent: 4338679 (1982-07-01), O'Toole
patent: 4355377 (1982-10-01), Sud et al.
patent: 4539661 (1985-09-01), Oritani

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