Self-timed digital circuits using linking circuits

Details Self-timed digital circuits using linking circuits Self-timed digital circuits using linking circuits

1994-06-03

1995-09-12

Hudspeth, David R.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

326 46, H03K 19003

Patent

active

054500206

DESCRIPTION:

BRIEF SUMMARY
This invention relates to linking circuits, particularly to linking asynchronous digital circuits, in such a way as to prevent further operation if a fault occurs. The invention is also concerned with apparatus formed by linking digital circuits in a particular way.
Integrated circuit technology has revolutionized electronic design but severe electrical design problems restrict the use of lower levels of integration. One of the foremost difficulties is the distribution of a high speed and accurate clock that can operate with the sub-nanosecond intervals required by the sub-micron technology. The regular array style of design considered suitable for Very Large Scale Integration (VLSI), complicates the clock distribution because of the large fan-out required to drive the large number of synchronous cells. The much higher speed of Gallium Arsenide circuits means that with even lower levels of integration, clock distribution can still limit the performance.
When a VLSI synchronous circuit is implemented using CMOS technology, the power spike that results from power consumption being focussed on clock edges introduces several electrical noise problems leading to intermittent faults.
Eliminating the clock requires an alternative method of identifying when the data is valid; typically a data ready/acknowledge protocol is used. The data ready signal is realized through a dual rail coding method where each single bit is manifest by a signal change on one of the two connections that form an individual signal path.
Circuits which do not need clock signals to synchronize themselves are known as self-timed circuits. Such circuits operate at the average circuit delay rate, unlike synchronous circuits which have to operate at the speed of the slowest component. Self-timed circuits also spread the switching of circuits, leading to lower peak power requirements.
Testing complex digital circuits is expensive and time-consuming since each element within the circuit must be tested with every possible combination of data values. Testing of self-timed circuits is also constrained because not every "stuck at" fault (that is a fault in which a connection is stuck at a steady voltage) is detected. There may be a large number of potential stuck at faults, making this problem more difficult.
It is an object of this invention to provide circuits which link functional logic circuits in a way which indicates the presence of stuck at faults by ceasing to provide output signals.
According to a first aspect of the invention there is provided a linking circuit for transmitting data values represented by code values, the code values being represented in the linking circuit by different states of a predetermined finite state machine, none of these states having a transition to itself, each state being represented by a combination of logic values and all transitions between states requiring a change in predetermined number of the logic values, the linking circuit comprising first and second inputs, an output and holding means for holding a state representing a code value received at the first input if the code values applied to the first and second input represent different states of the finite state machine, and the transition to the state received from the state currently held by the holding means is a legitimate transition as defined by the finite state machine.
Linking circuits may be used to couple functional logic circuits in achieving the above objects. One or two linking circuits alternating with logic circuits can provide a self-timed arrangement. Not passing a data state to its output, unless a legitimate transition is involved and inputs of preceding and succeeding linking circuits are in different states, allows such a self-timed arrangement to be operated and causes the arrangement to lock-up, stopping its output data stream if a stuck at fault occurs.
Restricting the finite state machine to one in which states which represent data do not have transitions to themselves allows the linking circuit to function when two or more succe

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