Self timed address locking and data latching circuit

Details Self timed address locking and data latching circuit Self timed address locking and data latching circuit

1995-12-04

1996-10-22

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518908, 365193, 36523008, G11C 700, G11C 800

Patent

active

055684300

ABSTRACT:
This invention provides an address locking and data latching timing control circuit for use in DRAMs using Extended Data Out (EDO) mode. The Extended Data Out (EDO) mode reduces the page mode cycle time with the same data period. This can result in loss of data if the data is not fully established and latched before the next column address arrives. The address locking and data latching timing control circuit of this invention locks the address input buffer and latches the data output buffer until the data is fully established and latched.

REFERENCES:
patent: 5488581 (1996-01-01), Nagao et al.
patent: 5490114 (1996-02-01), Butler et al.

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