Self-Test pattern to detect stuck open faults

Details Self-Test pattern to detect stuck open faults Self-Test pattern to detect stuck open faults

2000-10-02

2002-08-27

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S189080, C365S230060

Reexamination Certificate

active

06442085

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the testing of integrated circuits and, in particular, to a logic pattern implemented by a Built-In Self-Test (BIST) that fully tests static decoders (decoders comprised of static CMOS logic elements) in a compilable static random-access memory (SRAM) architecture.
BACKGROUND OF THE INVENTION
Existing “unique address” BIST logic patterns test the SRAM by accessing each memory cell in a sequential incrementing address or decrementing address pattern. These patterns are used because they are exhaustive in that they access every cell address in the design as well as being very easily implemented in an on-chip BIST circuit. For each cell access, a logic value is read, then the opposite logic value is written and read. Unfortunately, these patterns do not filly test the static address decoder logic inside the SRAM, as will become clear from the following.
A simple prior art three-bit static decoder, implemented as a three-input NAND (
FIG. 1
a
) decoder in complementary MOS (CMOS) logic, is shown in
FIG. 1
b
. Output Z of
FIG. 1
b
is a logical “0” when inputs A
0
, A
1
, and A
2
are all at a logical “1”. The output Z is a logic 1 value for all other combinations of the inputs. A traditional sequential addressing pattern, for the decoder of
FIG. 1
b
, is shown in
FIG. 2
, where A
0
is the least significant bit (LSB). As shown in the incrementing address sequence of
FIG. 2
, the only transitions that cause the output Z to change logical state are from cycle
7
to
8
, (A), and from cycle
8
to
9
, (B). All of the n-channel field effect transistors (NFETs) must be functional to cause Z to transition to a logical “0”. However, for the output Z to transition from a logical 0 to a logical 1, only one functional p-channel FET (PFET) is needed, as shown by transition (B). Either of the other two remaining PFETs could be “stuck open” and this test pattern would not detect them. The reason the “stuck open” fault would not be detected is described by example in the following paragraph.
Suppose PFET P
2
, as shown in
FIG. 1
a
, is defective due to a “stuck open” fault and PFETS P
0
and P
1
function properly. During cycle
4
, listed in the table of
FIG. 2
, the logic values assigned to bits A
0
-A
2
will cause PFETS P
0
and P
1
to stop conducting current between their respective drain and source leads. In other words, P
0
and P
1
will become open circuited. PFET P
2
is intended to conduct current, thereby allowing the higher potential rail voltage, less the small drain-to-source voltage drop, to develop on the output Z. However, because P
2
has a “stuck-open” fault, the PFET does not conduct current between its drain and source and, therefore, cannot support the development of a voltage potential at output Z. This situation does not necessarily cause the output Z to transition to a logical 0 state, though. During cycle
3
, output Z has a voltage potential representing a logical 1 and this potential will charge the parasitic capacitances of the FETs. The parasitic resistances of the FETs will not discharge the stored energy quickly enough to cause the output Z to reflect a logical 0, in some instances. In such an instance, only a conductive path between output Z and the lower potential rail voltage could discharge the stored energy sufficiently quickly to generate a logical 0 on output Z. During cycle
4
, however, the NFET connected to A
2
, and in series with the two other NFETs, prevents the flow of current between the output Z and the lower potential rail. Therefore, the “stuck open” fault affecting P
2
would not be detected by the test sequence shown in the table of FIG.
2
. Similarly, a “stuck open” fault affecting any other PFET or any two PFETs may not be detected by the test sequence.
Again, for the three-input NAND gate, the decrementing address sequence of
FIG. 3
shows that the output Z changes its logical state only during the transition from cycle
1
to cycle
2
, (A), and from cycle
8
to cycle
9
, (B). Transition (B) will fully test the NFETs, since all
3
NFETs are required to be functional for the output Z to change to a logical “0.” Transition (A) requires only one PFET (specifically device P
0
) to be functional for the output Z to change to a logical “1” state. Devices P
1
and P
2
could have “stuck open” faults and this test sequence would not detect them, for the same reason described in the preceding paragraph.
This problem also exists for a NOR decoder. A three bit NOR decoder is shown in
FIGS. 4
a
and
4
b
. The output Z is a logic 1 value when inputs A
0
, A
1
, and A
2
are all at logic 0 values. The output Z is a logic 0 value for all other combinations of the inputs. An ascending sequential addressing pattern is shown in
FIG. 5
, where A
0
is the least significant bit (LSB). As shown in
FIG. 5
, the only transitions that cause the output Z to change logic states are from cycle
1
to
2
, (A), and from cycle
8
to
9
, (B). All three PFETs must be functional to transition the output Z from 0 to 1. In transition (A), the only NFET being tested is NO. A “stuck-open” fault in N
1
or N
2
will go undetected by this test. Again, for the descending pattern, only one NFET must be functional and either of the other two may have “stuck-open” faults, which would go undetected, as shown in FIG.
6
. The reason these “stuck open” faults would not be detected is explained by example in the following paragraph.
Suppose NFET N
2
, as shown in
FIG. 4
a
, is defective due to a “stuck open” fault and NFETS N
0
and N
1
function properly. During cycle
5
, listed in the table of
FIG. 5
, the logic values assigned to bits A
0
-A
2
will cause NFETS N
0
and N
1
to stop conducting current between their respective drain and source leads. In other words, N
0
and N
1
will become open circuited. NFET N
2
is intended to conduct current, thereby allowing output Z to develop the voltage of the lower potential rail, plus the small drain-to-source voltage drop. However, because N
2
has a “stuck-open” fault, the NFET does not conduct current between its drain and source and, therefore, cannot discharge the energy stored by the parasitic capacitances of the FETs quickly enough in some instances. This situation does not necessarily cause the output Z to transition to a logical 1 state, though. During cycle
4
, output Z has a voltage potential representing a logical 0 and this potential determines the charge stored by the parasitic capacitances of the FETs attached to output Z. The PFETs connected to A
0
and A
1
, and in series with PFET A
2
, prevent the flow of current between the output Z and the higher potential rail. As a result, the output Z will tend to maintain the logical 0 state since no conductive path exists to the higher potential rail. Therefore, the “stuck open” fault affecting N
2
would not be detected by the test sequence shown in the table of FIG.
5
.
The sequential addressing patterns (both the increment and decrement) do not test devices P
1
and P
2
in the NAND and devices N
1
and N
2
in the NOR. The traditional unique address pattern used during a self-test operation is sequential. However, during normal functional operation the SRAM is accessed randomly. It was shown above that the SRAM would pass a sequential pattern, generated by an on-chip BIST, even when certain decoder devices are failing. However, these failures may be exhibited in normal operation, resulting in non-functional customer hardware. Therefore, it is imperative that these “stuck-open” faults be detected during a manufacturing test.
Application specific integrated circuit (ASIC) products create a number of very unique concerns. The nature of ASIC products is such that unique circuit designs may be readily developed during the market-life of an ASIC technology library, with each design different from the rest and developed for a highly specific use. Also, the SRAMs, which appear in these ASIC chips, may be configured to the customers'size and area needs. Because of the large number of chip designs

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