Self test of plesiochronous interconnect

Details Self test of plesiochronous interconnect Self test of plesiochronous interconnect

2007-07-06

2011-11-22

Rizk, Sam (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error detection for synchronization control

C708S250000

Reexamination Certificate

active

08065597

ABSTRACT:
A method and apparatus for performing a self-test of a plesiochronous link. A pseudorandom serial bit pattern is generated by the transmitter from a linear feedback shift register (LFSR) based on a primitive polynomial of a specific order and transmitted across a plesiochronous link. Bits of this transmitted pattern are received and deserialized into n parallel bits. In the receiver, given the current n bits in the bit pattern, the next n bits that are expected in the bit pattern are computed in advance. The next n compare bits thus generated are delayed and compared when the next n bits from the transmitted pattern arrive at the receiver and an error is signaled in the case of a mismatch. The method further repeats the receiving, deserializing and computing the next expected bits for each n bits of the received pattern.

REFERENCES:
patent: 2005/0071399 (2005-03-01), Bonaccio et al.
patent: 2008/0114562 (2008-05-01), Sul et al.
Braden, et al., “Use of BIST in Sun Fire Servers,” Test Conference Proceedings International 2001, Baltimore, Maryland, pp. 1017-1022.
“PCI Express Base Specification Revision 2.0,” PCI Express, Dec. 20, 2006, pp. 191-237.
Hamdioui, et al, “Testing Static and Dynamic Faults in Random Access Memories,” Proceedings of the 20th IEEE VLSI Test Symposium (VTS '02), pp. 1-6.

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