Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
1998-12-29
2001-08-14
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C396S029000, C396S095000, C327S175000, C327S291000
Reexamination Certificate
active
06275069
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates logic circuits and methods of operation thereof, and more particularly, to self-resetting logic circuits and methods of operation thereof.
BACKGROUND OF THE INVENTION
Dynamic logic circuits typically perform logic operations using properties of capacitive storage nodes. Such logic circuits are commonly utilized in processor logic, and are now being utilized in memory circuits.
The operations of a typical dynamic logic circuit fall into two distinct phases: a precharge phase and an evaluation phase. A clock signal provides logic synchronization and also allows predefined charge states to be established in a precharge phase of the clock cycle. One or more outputs are produced during a predetermined evaluation portion of the clock cycle.
Dynamic logic circuits are often contracted from complementary metal oxide semiconductor (CMOS) field effect transistors, due to their low power dissipation. A logic cell commonly used in dynamic CMOS logic circuits includes a precharge device (usually a single PMOS transistor) with a clock input to which a periodic clock signal is applied, a logic circuit (usually an NMOS circuit) with one or more logic inputs for receiving input signals, and an evaluation device (usually a single NMOS transistor) with a clock input for receiving the clock signal. During a precharge phase, the clock signal is at a logic low state (“0”), such that an output is connected to a supply voltage (V
DD
) through the PMOS precharge transistor and precharged to a logic high (“1”) state. The evaluation phase occurs when the clock signal transitions to a logic high state, turning off the PMOS precharge transistor and turning on the NMOS evaluation transistor. Depending on the input signal value(s), the output either is discharged to a logic low state or remains at a logic high state.
Thus, as described above, a typical dynamic logic circuit is driven by a clock signal to synchronize and to effect the associated logical function implemented in the logic circuit. The clock signal also serves to precharge the logic circuit so that it is ready for the next series of signal inputs.
One problem with utilizing a clock signal to synchronize logical operations within an integrated circuit, which may include logic circuits cascaded as a plurality of stages, is that the clock signal may be subject to noise and clock skew while being transmitted throughout the integrated circuit, resulting in a distorted and inaccurate response at a given one of the cascaded logic circuits.
A proposed solution to the foregoing problem is to combine a reset circuit with a logic circuit, the reset circuit being operative to precharge the logic circuit to a ready state so that it can accept input signals and responsively perform logical operations in a coordinated fashion. Examples of such conventional self-resetting dynamic CMOS logic circuits are described in U.S. Pat. No. 4,751,407 to Powell, U.S. Pat. No. 5,465,060 to Pelella, U.S. Pat. No. 5,467,037 to Kumar et al., U.S. Pat. No. 5,543,735 to Lo, U.S. Pat. No. 5,550,490 to Durham et al., U.S. Pat. No. 5,576,644 to Pelella, and U.S. Pat. No. 5,650,733 Covino.
The output signal produced by such a self-resetting circuit may be directly affected by the input pulse width. When such self-resetting dynamic logic circuits are cascaded in a plurality of stages in an integrated circuit such as a processor or memory, there may be a need to provide a reset (or precharge) timing margin for each circuit in order to guarantee stable reset operation. Along a cascade of stages, the need to provide a reset margin may cause respective stage output pulse widths to undesirably increase down the chain of stages. For this and other reasons, it may be difficult to control the timing of the integrated circuit.
SUMMARY OF THE INVENTION
In light of the foregoing, it is an object of the present invention to provide self-resetting logic circuits and methods of operation thereof that exhibit improved timing control.
It is another object of the present invention to provide self-resetting logic circuits and methods of operation thereof suitable for high-speed applications.
It is yet another object of the present invention to provide self-resetting logic circuits and methods of operation thereof exhibiting stable operation.
These and other objects, features and advantages are provided according to the present invention by self-resetting logic circuits and methods of operation thereof in which a logic circuit is combined with a reset circuit that is triggered to reset an output signal produced by the logic circuit responsive to state transition of the output signal within a first predetermined interval, and which can be armed responsive to a state transition of an input signal to the logic circuit within a second predetermined interval that is substantially less than the first predetermined interval. The reset circuit preferably includes a bistable circuit that has a set input that is responsive to the output signal from the logic circuit and a reset input that is responsive to the input signal to the logic circuit, the bistable circuit producing an output signal that is coupled to a reset input node of the logic circuit that controls resetting of the logic circuit.
Self-resetting logic circuits and methods of operation thereof according to the present invention offer several advantages over conventional self-resetting circuits. Because the delay in rearming the reset circuit can be made much shorter than that involved in resetting the output of the logic circuit, self-resetting circuits according to the present invention can tolerate high-speed input signals, and do not require inordinately large reset timing margins. Accordingly, self-resetting logic circuits according to the present invention are well suited for cascaded high-speed logic operations in devices such as processors and memories.
In particular, according to the present invention, a self-resetting circuit includes a logic circuit operative to transition an output signal from a first logic state to a second logic state responsive to a first logic state transition of an input signal, along with a bistable reset circuit coupled to the logic circuit and operative to be triggered by the transition of the output signal from the first logic state to the second logic state to reset the output signal to the first logic state within a first predetermined interval following the transition of the output signal from the first logic state to the second logic state, and to be armed by a second logic state transition of the input signal next succeeding the first logic state transition, wherein the reset circuit is armed within a second predetermined interval following the second transition that is substantially less than the first predetermined interval.
According to embodiments of the present invention, the logic circuit has an input node configured to receive the input signal, and a reset input node and an output node, and is operative to produce a transition in the output signal at the output node responsive to the input signal when the reset input node is at a first one of the first and second logic states and to reset the output signal to the first logic state when the reset input is at a second one of the first and second logic states. The bistable reset circuit has a first input node coupled to the output node of the logic circuit, a second input node coupled to the input node of the logic circuit, and an output node coupled to the reset input node of the logic circuit, and is operative to set the reset input node of the logic circuit to the first one of the first and second logic states responsive to the input signal and to set the reset input node of the logic circuit to the second one of the first and second logic states responsive to the output signal.
In another embodiment according to the present invention, a self-resetting circuit includes a logic circuit having an output node, an input node and a reset input node and operative to transition an output signal at the out
Chung Min-Chul
Jung Chul-Min
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Tokar Michael
Tran Anh
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