Self refresh circuit of PSRAM for real access time...

Details Self refresh circuit of PSRAM for real access time... Self refresh circuit of PSRAM for real access time...

2007-03-06

2007-03-06

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S195000, C365S233100

Reexamination Certificate

active

11261152

ABSTRACT:
A self refresh circuit includes a refresh control unit and an internal refresh circuit. The refresh control unit generates a refresh control signal based on a refresh period pulse when a MRS (Mode Set Register) command is deactivated, interrupts an output of the refresh control signal based on a self-refresh-entrance inhibiting signal when the MRS command is deactivated, and generates a refresh command regardless of the refresh period pulse when the MRS command is activated. The MRS command is generated by a combination of at least one address signal and at least one control signal. The internal refresh circuit performs a refresh operation based on the refresh command. Accordingly, access time may be measured correctly and test time may be reduced.

REFERENCES:
patent: 6567339 (2003-05-01), Bando
patent: 6721223 (2004-04-01), Matsumoto et al.
patent: 6879536 (2005-04-01), Lee
patent: 2004/0027900 (2004-02-01), Lee
patent: 2002-093163 (2002-03-01), None
patent: 10-2003-0009080 (2003-01-01), None
patent: 10-2004-0014838 (2004-02-01), None

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