Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2000-06-27
2001-07-03
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Precharge
C365S222000
Reexamination Certificate
active
06256244
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a self refresh apparatus in a semiconductor memory device, and more particularly to a self refresh apparatus for conducting a self refresh operation in a semiconductor memory device using a shared sense amplifier system.
2. Description of the Related Art
In a semiconductor memory device such as a DRAM, a memory cell thereof generally includes one capacitor and one MOS transistor. In such a configuration, there may be a problem in that a leakage of current may occur at a PN junction of the MOS transistor, so that the charge initially stored in the capacitor is lost, thereby causing a loss of data.
To this end, a refresh operation is periodically conducted before data is lost. In accordance with the refresh operation, data is read from the memory cell, and a recharge is carried out up to the initial amount of charges for the read data.
FIG. 1
is a block diagram illustrating a conventional self refresh apparatus in a DRAM using a shared sense amplifier system.
As shown in
FIG. 1
, the self refresh apparatus includes a refresh counter
10
for receiving an external clock signal CLK in a self refresh mode, and outputting word line selection signals WSA and cell block selection address signals BSAU and BSAD in response to the received clock signal CLK. The clock signal CLK is a signal for changing the state of the refresh counter
10
for every self refresh cycle. The cell block selection address signals BSAU and BSAD are adapted to select an up cell block
20
and a down cell block
22
, respectively.
The self refresh apparatus also includes a block selection unit
12
for receiving a precharge signal PRECHG and the address signal BSAU, and outputting a word line activation signal BSXU, based on the received signals. The word line activation signal BSXU serves to activate the word lines of the up cell block
20
. A block selection unit
14
is also provided which receives the precharge signal PRECHG and the address signal BSAD, thereby outputting a word line activation signal BSXD serving to activate the word lines of the down cell block
22
.
The self refresh apparatus further includes a sense amplifier selection unit
16
which receives the word line activation signals BSXU and BSXD respectively from the block selection units
12
and
14
, and connects a selected one of the up and down cell blocks
20
and
22
to sense amplifiers included in a sense amplifier array
18
.
As shown in
FIG. 2
, the sense amplifier selection unit
16
includes an inverter IV
1
for inverting the word line activation signal BSXD for the down cell block
22
, and an NMOS transistor N
1
switched on or off in response to the inverted signal outputted from the inverter IV
1
, thereby selectively generating an output signal as a signal BISU adapted to enable a connection between the up cell block
20
and the sense amplifiers. The sense amplifier selection unit
16
also includes an inverter IV
2
for inverting the word line activation signal BSXU for the down cell block
22
, and an NMOS transistor N
2
switched on or off in response to the inverted signal outputted from the inverter IV
2
, thereby selectively generating an output signal as a signal BISD adapted to enable a connection between the down cell block
22
and the sense amplifiers. The sense amplifier selection unit
16
further includes a pair of PMOS transistors P
1
and P
2
connected in series between output terminals of the sense amplifier selection unit
16
from which the signals BISU and BISD are outputted, respectively. A high voltage source VPP is coupled to a node A
1
between the PMOS transistors P
1
and P
2
. A NAND gate ND
1
is coupled at an output terminal thereof to respective gates of the PMOS transistors P
1
and P
2
. The NAND gate ND
1
serves to carry out a NANDing operation for the signals BSXU and BSXD.
When the signals BXSU and BSXD, each of which initially has a high level, are inputted to the sense amplifier selection unit
16
, the NAND gate ND
1
outputs a low-level signal in response to the input signals BSXU and BSXD. In accordance with the low-level signal from the NAND gate ND
1
, both the PMOS transistors P
1
and P
2
turn on, thereby generating output signals having the same level as that of the high voltage source VPP as the signals BISU and BISD. When only one of the input signals BSXU and BSXD, for example, the input signal BSXU adapted to activate the word lines of the up cell block
20
, is switched to a low level, the NMOS transistor N
2
is rendered to turn on. As a result, the level of the output signal BISD is switched to a ground voltage level. At this time, the NMOS transistor N
1
is turned off, so that the output signal BISU is maintained at a high voltage level. On the other hand, both the PMOS transistors P
1
and P
2
are turned off because the output signal from the NAND gate ND
1
has a high level. In this state, accordingly, the up cell block
20
is connected to the sense amplifiers.
The above mentioned operation is associated with the connection between the up cell block
20
and the sense amplifiers. The operation for the connection between the down cell block
22
and the sense amplifiers is carried out in a manner similar to that of the above-mentioned operation.
Now, the operation of the self-refresh apparatus will be described with reference to a timing diagram illustrated in FIG.
3
.
The clock signal CLK has a clock pulse of a desired width generated every time the precharge signal PRECHG is switched to its disable state. This clock signal CLK is inputted, as a control signal, to the refresh counter
10
. In response to every clock pulse of the clock signal CLK, the refresh counter
10
increments an address value by one. The refresh counter
10
generates the cell block selection address signals BSAU and BSAD when it counts a predetermined number of clock pulses, and outputs those cell block selection address signals BSAU and BSAD to the block selection units
12
and
14
, respectively.
The block selection unit
12
carries out an ANDing operation for the cell block selection address signals BSAU and the precharge signal PRECHG, thereby generating an output signal, namely, the signal BSXU, which is, in turn, applied to the sense amplifier selection unit
16
. On the other hand, the block selection unit
14
carries out an ANDing operation for the cell block selection address signals BSAD and the precharge signal PRECHG, thereby generating an output signal, namely, the signal BSXD, which is, in turn, applied to the sense amplifier selection unit
16
.
The sense amplifier connect signals BISU and BISD, which are outputted from the sense amplifier selection unit
16
, selectively have a high level in accordance with a computation conducted in the sense amplifier selection unit
16
. In response to the sense amplifier connect signal BISU or BISD having a high level, a corresponding one of the cell blocks
20
and
22
is coupled to the sense amplifiers.
For instance, when the precharge signal PRECHG is switched to its disable state under the condition in which the cell block selection address signal BSAU is in an active state, the signal BSXU outputted from the block selection unit
12
is rendered to be active, thereby causing the signal BISU outputted from the sense amplifier selection unit
16
to be active. In this state, bit lines BITU and BITBU of the up cell block
20
are connected to an associated one of the sense amplifiers which, in turn, conducts a sensing operation for an associated one of the cells in the up cell block
20
, thereby refreshing the associated cell. When the precharge signal PRECHG is switched to its active state after the refresh of the cells, the signal BSXU is switched to its disable state, thereby causing the signal BISU to be switched to its disable state.
Similarly, when the precharge signal PRECHG is switched to its disable state under the condition in which the cell block selection address signal BSAD is in an active state, the signal BISD outputted from
Hyundai Electronics Industries Co,. Ltd.
Le Vu A.
Nath Gary M.
Nath & Associates PLLC
Phung Anh
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