Self-invalidation method for reducing coherence overheads in a b

Details Self-invalidation method for reducing coherence overheads in a b Self-invalidation method for reducing coherence overheads in a b

1996-07-12

1998-11-10

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711145, G06F 1300

Patent

active

058359508

ABSTRACT:
The present invention relates to a method for reducing overheads of cache coherence enforcement in a shared-bus multiprocessors apparatus by utilizing a self-invalidation technique at local processor nodes as an extension to write-invalidate protocols in the shared-bus environment, and to an apparatus therefor.

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patent: 5623628 (1997-04-01), Brayton et al.
patent: 5737755 (1998-04-01), Ebrahim et al.
Anderson, C. et al. "Two Techniques for Improving Performance on Bus-Based Multiprocessors", Proceedings of the First IEEE Symposium on High-Performance Computer Architecture, pp. 264-275 Jan. 1995.
Lebeck, A. et al. "Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors", Computer Architecture News, pp. 48-59 May 1995.
Dahlgren, F. "Boosting the Performance of Hybrid Snooping Cache Protocols", Computer Architecture News, pp. 60-69 May 1995.
Hennessy, J. et al. Computer Architecture: A Quantitative Approach, pp. 467-474 1990.

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