Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
1997-03-03
2001-02-06
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S156000, C365S189020
Reexamination Certificate
active
06185126
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to programmable logic devices and, more particularly, to programmable logic devices employing volatile programmable cells for use in configuring desired logic functions.
BACKGROUND
Programmable logic devices (PLDs) are popular general purpose logic devices. Traditional PLDs generally include a number of logic elements (e.g., in the form of logic cells or a logic array) and a number of input/output (I/O) macrocells. A routing interconnect is used to transport electrical signals from input macrocells to selected logic elements. The logic elements typically provide a number of logical AND and logical OR functions which are combined to create a number of output signals, called sum of product expressions. The signals generated by the logic elements are then passed to macrocells which typically include register elements. The macrocells are coupled to output pads for transferring the logic signals out of the PLD and also may also be coupled to signal paths which feed back the logic signals to further logic elements to create even more complex logic signals.
These programmable logic devices are capable of implementing various logic functions by selectively coupling the electrical signals within the device to desired logic elements (e.g., AND gates, OR gates, etc.). Selected logic paths for the electrical signals can be implemented by programming appropriate elements in the routing interconnect. Typically, these programmable elements are non-volatile, that is, once programmed the elements retain their respective programmed states even when power is removed from the device.
Some families of programmable logic devices such as PLDs, complex PLDs (so-called CPLDs) and field programmable gate arrays (FPGAs) have replaced traditional programmable elements (e.g., fuses, antifuses, EPROM cells, EEPROM cells and flash cells) with volatile, i.e., RAM (random access memory), elements. So-called RAM-based FPGAs (and other RAM-based programmable logic devices) implement logic gates and/or programmable interconnect points with volatile RAM cells which lose their programmed (or stored) state when power is turned off. As a result, RAM-based FPGAs must be programmed after power-up with the appropriate stored states for each RAM cell to configure the desired logic functions. These stored states are typically loaded via a serial interface from a non-volatile storage source such as a companion EPROM or EEPROM device which maintains its stored contents when the power supply is removed. Alternatively, RAM-based FPGAs may be configured by loading the stored states for the desired logic function from a magnetic disc source via a microcontroller or by another means.
Regardless of the method used to program the RAM cells of the FPGA, there is a delay after power-up before the logic can be utilized by other elements in the system in which the device operates. Consequently, RAM-based FPGAs cannot be used to implement those portions of a system which control initialization upon power-up. Further, the non-volatile storage devices used to store the configuration program for such RAM-based FPGAs require additional system overhead (including space on a printed circuit board in those systems so designed).
Accordingly, what is needed is a means for setting the power-up state of some or all of the storage elements in such a RAM-based FPGA or other programmable device to ensure that the proper stored state will be available immediately upon power up. In addition, it is also desirable to eliminate the need for a separate non-volatile storage device for programming such RAM-based programmable devices.
SUMMARY OF THE INVENTION
In one embodiment, the present invention provides a programmable logic device which includes a node and a RAM cell configured to power-up in a preferred state so as to provide a predetermined logic signal to the node upon power-up.
The node may comprise an interconnection element, for example a transistor. Associated with the interconnection element may be two signal lines within the programmable logic device, for example, as part of a programmable interconnect matrix. The interconnection element and the two signal lines are associated such that when the interconnection element is in a first state the two signal lines are electrically coupled and when the interconnection element is in a second state the two signal lines are not electrically coupled. The predetermined logic signal from the RAM cell selects one of the first and second states.
In another embodiment, the RAM cell may include two PMOS transistors, each having an associated threshold voltage, wherein the threshold voltage of one of the PMOS transistors is lower than the threshold voltage of the other PMOS transistor. The RAM cell may be included in a look-up table such that the node is an output of the look-up table.
In yet another embodiment, the programmable logic device may further include a multiplexer wherein the RAM cell is coupled to the multiplexer through the node.
In a further embodiment, the present invention provides a method of programming a programmable logic device by applying power to the device and powering up a RAM cell in a preferred state so as to provide a predetermined logic signal to a node within the device.
These and other features and advantages of the present invention will be apparent to those skilled in the art upon review of the detailed description below and the figures referenced therein.
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Graf, III W. Alfred
Rodgers T. J.
Cypress Semiconductor Corporation
Dinh Son T.
Wagner , Murabito & Hao LLP
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