Self-gating synchronizer

Details Self-gating synchronizer Self-gating synchronizer

2011-07-12

2011-07-12

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Metastable state prevention

C326S093000, C326S095000, C326S096000

Reexamination Certificate

active

07977976

ABSTRACT:
A synchronizer circuit for transferring data from a source clock domain to a target clock domain. A first latch in the target clock domain may capture a data value corresponding to current data received from the source clock domain. Under certain conditions, the first latch may enter into a metastable, or undefined logic state. A second latch may remain stable, and store a previous value corresponding to data that has most recently been transferred from the source clock domain to the target clock domain. The respective values output by the two latches may be compared by a detection circuit, and a value derived from the output value of the first latch and corresponding to the current data may be written to an output latch if the current data differs from the stored previous value. The detection circuit may also provide a defined logical value to the output latch even if the first latch is in a metastable state.

REFERENCES:
patent: 7091742 (2006-08-01), Ryan
patent: 7795921 (2010-09-01), Tanaka
patent: 7843244 (2010-11-01), Tang et al.
patent: 2008/0101513 (2008-05-01), Zhu et al.
patent: 2009/0153202 (2009-06-01), Yagi
patent: 2009/0238317 (2009-09-01), McCabe
patent: 2009/0315601 (2009-12-01), Priel et al.

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