Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-12-20
2004-01-13
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06678875
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, in general, to the design of integrated circuits and, more specifically, to a framework or workspace for use in the design, verification and integration of circuits and to an environment setup utility for automating the creation of the framework.
2. Description of Related Art
As integrated circuits continue to become increasingly more complex, it is becoming increasingly more important to embed into the circuits test structures which can be used during and after manufacture to test the circuit and its various sub-circuits and components. The generation and integration of these test structures is complex and tedious because a circuit may required many specialized test structures and include embedded circuit blocks which also require test structures. By way of example,
FIG. 1
illustrates a relatively simple test ready circuit
10
having a variety of embedded test structures. The circuit includes an embedded circuit block
12
which has logic
14
, a DRAM
16
, and a legacy core
18
. The test structures which are embedded in embedded block
12
include a logic BIST controller
20
associated with logic
14
, a memory test controller
22
associated with DRAM
16
and a core socket
24
which provides isolation and access to legacy core
18
. The top module
30
of circuit
10
includes logic
32
, two memory units, including a SRAM
34
and ROM
36
, a phase locked loop (PLL)
38
, an analog-to-digital converter (ADC)
40
and a number of circuit input and output pins. The test structures which were added to the top module include a logic test controller
42
associated with logic
32
, a memory test controller
44
associated with SRAM
34
and ROM
36
, a phase locked loop test controller
46
associated with PLL
38
, an ADC test controller
48
associated with ADC
40
, interconnect test controllers
50
,
52
, and
54
, and a test access port (TAP)
56
connected to the various test controllers. In addition, non-scannable memory elements in each of the embedded block and the top module were converted to scannable memory elements and arranged into scan chains. Test vectors and test patterns were generated and stored during the course of designing and integrating the test structures in the circuit block.
The embedded test structures are used cooperatively for testing sub-blocks, which may be buried deep within an embedded block, from the circuit pins such as the test access port.
Automation tools, available from the patentee, LogicVision, Inc. of San Jose, Calif., may be used to generate and verify the test structures and assemble them into a circuit description of a circuit under development. Generally, each test structure has a respective, specialized set of automation tools which provide several optional features, which or may not be included, depending on the desires of the designer. Thus, In addition to the complexity of the circuit itself and of the test structures which must be designed into the circuit, a designer faces the complexity of operating various automation tools which must be used to analyze the circuit, create the appropriate test structures, create test vectors and patterns to test the circuit, verify the test structures and perform all of the many and varied tasks which must be performed to provide a test ready circuit. The automation tools necessarily generate a relatively, large number of electronic files which must be stored, managed and accessed during the design-for-test process.
Applicant is not aware of any system or framework which has been proposed for organizing the many electronic files which are created by design-for-test procedures and operations, or of a utility for creating such a framework based on the specific needs and desires of a circuit designer. There is a need for both a design-for-test framework for use in storing embedded test structure related files and a environment setup utility for creating a design-for-test framework.
SUMMARY OF THE INVENTION
The present invention seeks to provide a self-contained design environment for storing files associated with the design of circuits and a setup utility for generating the design environment based on the specific needs of the circuit designer.
One aspect of the present invention is generally defined as a program product for use in creating a self-contained, design-for-test workspace on a computer readable storage medium for storing design-for test files associated with a circuit block, comprising means for generating a circuit block repository on the storage medium, the circuit block repository including a repository for each of predetermined design flows; process control file generating means for generating a process control file for selected repositories for use in performing predetermined operations; and means for creating links to repositories for circuit design files, library files and databases of blocks embedded in the circuit block.
Automated Benefits
Using the utility to implement embedded test provides a number of major benefits. First, based on the user's input to the utility, the utility sets up the user's design environment automatically and according to intended design flow. The utility creates a directory structure or workspace and populates the directories with pertinent design data, including readme files that the utility creates to provide clear instructions on what the user needs to do to complete each step of the design process, and process control files generated by the utility to provide all the command-line runtime options and appropriate settings required to implement the embedded test design flow and, more specifically, to run specialized automation tools. Second, the starter templates generated by the utility provide all the input files required to run the full embedded test design flow as well as individual design phases within this flow. The starter templates require minimal editing by the user, if any. If a user chooses to use the default values when running the process control files, the user need not make any edits to the files. Third, all data is transferable at all levels. The user can transfer the entire design or only a level within the design hierarchy that is problematic. Data is transferable because the utility creates a design environment and a set of process control files that are all relative-that is, information that is not hard-coded.
Another aspect of the present invention relates to the workspace or framework for use in the design of a circuit. This aspect is generally defined as a self-contained, circuit design framework for use in a computer readable storage medium for storing files associated with designing a circuit block according to a design flow having a plurality of phases and using design automation tools for generating the test files, the framework comprising a circuit block repository having design environment repositories containing links to design library repositories and files so that all scripts referring to the repositories and files use a relative path to the links contained within the design environment repositories; a design flow repository for each phase of the plurality of design flow phases; a process control file in the circuit block repository and each design flow repository for use in performing predetermined operations; a process information file corresponding to each process control file and describing the operations; and a design flow configuration file in each of the circuit block and design flow repository for use in specifying design flow options and parameter values.
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patent: 6120550
Côté Jean-François
Pajak Brian John
Price Paul
Romain Luc
Liu Andrea
LogicVision, Inc.
Proulx Eugene E.
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