Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2011-04-26
2011-04-26
Lee, Thomas (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S501000, C712S001000, C712S040000
Reexamination Certificate
active
07934113
ABSTRACT:
A digital circuit may have at least two asynchronous clock domains with a controller responsive to a first domain clock signal and a target responsive to a second domain clock signal. A first domain control signal pulse is generated in response to the first domain clock signal for controlling the target. Each assertion the first domain control signal pulse is detected and used to form a second domain control signal pulse synchronized to the second domain clock signal. The target is controlled using the second domain control signal pulse. If the target is a clear-on-read register, contents of the clear-on-read register are latched in a feedback register in response to the first domain control signal pulse and provided to the controller. Each bit of the clear-on-read register is reset in response to the second domain control signal pulse only if the corresponding latched content of each bit in the feedback register is a logical one.
REFERENCES:
patent: 2001/0042219 (2001-11-01), Robertson
patent: 2006/0164902 (2006-07-01), Fung
Chard Gary Franklin
Koh T-Pinn Ronnie
Wang Yilun
Brady III Wade J.
Brown Michael J
Lee Thomas
Patti John J.
Telecky , Jr. Frederick J.
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