Self-aligned trench MOSFET structure and method of manufacture

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S197000, C438S299000, C257S331000, C257SE29146, C257SE29156

Reexamination Certificate

active

07452777

ABSTRACT:
A trench gate FET is formed as follows. A well region is formed in a silicon region. A plurality of active gate trenches and a termination trench are simultaneously formed in an active region and a termination region of the FET, respectively, such that the well region is divided into a plurality of active body regions and a termination body region. Using a mask, openings are formed over the termination body region and the active body region. Dopants are implanted into the active body regions and the termination body region through the openings thereby forming a first region in each active and termination body region. Exposed surfaces of all first regions are recessed so as to form a bowl-shaped recess having slanted walls and a bottom protruding through the first region such that remaining portions of the first region in each active body region form source regions that are self-aligned to the active gate trenches.

REFERENCES:
patent: 2004/0195620 (2004-10-01), Chuang et al.
patent: 2005/0079676 (2005-04-01), Mo et al.
patent: 2005/0167742 (2005-08-01), Challa et al.
patent: 2005/0224891 (2005-10-01), Xu
International Search Report and Written Opinion of the ISA, PCT/US06/61687, mailed Sep. 2, 2008, 9pp.

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