Self-aligned source/drain mask ROM memory cell using trench etch

Details Self-aligned source/drain mask ROM memory cell using trench etch Self-aligned source/drain mask ROM memory cell using trench etch

1996-09-16

1998-05-12

Monin, Donald

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257390, 257394, 257401, H01L 2702, H01L 2710

Patent

active

057510407

ABSTRACT:
A device and a method are provided for manufacture of that semiconductor memory device on a silicon semiconductor substrate with a vertical channel. A dielectric layer pattern with openings through it is formed. Trenches are formed in the surface of the semiconductor substrate. The trenches have sidewalls. A spacer layer is formed on the surface of the device. The spacer layer is shaped to form spacers in the trenches on the sidewalls. Source/drain regions are formed by ion implanting ions to deposit dopant into the substrate. The device is annealed to form source/drain regions in the substrate. A dielectric layer is formed over the device. A conductive word-line is formed and patterned over the dielectric layer.

REFERENCES:
patent: 5244824 (1993-09-01), Sivan
patent: 5288666 (1994-02-01), Lee
patent: 5300804 (1994-04-01), Arai
patent: 5338953 (1994-08-01), Wake

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