Self-aligned silicide process for reduction of Si...

Details Self-aligned silicide process for reduction of Si... Self-aligned silicide process for reduction of Si...

2001-02-21

2002-09-03

Fahmy, Jr., Wael (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S655000, C438S597000, C438S630000

Reexamination Certificate

active

06444578

ABSTRACT:

DESCRIPTION
Field of the Invention
The present invention relates to a method of forming ohmic contacts for a semiconductor device, and more particularly to a self-aligned silicide process, i.e., salicide process, which substantially minimizes silicon (Si) consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.
BACKGROUND OF THE INVENTION
As the miniaturization of microelectronic devices progresses, it is becoming increasingly difficult to form low resistivity (on the order of 25 &mgr;ohm·cm or below) silicide contacts to the source, drain and gate of the transistor. In the next generation of devices and beyond, one of the major challenges for silicidation is to keep the low resistivity of the silicide by maintaining its thickness, while reducing consumption of Si during silicidation. Since the dopant distribution is now extremely shallow (on the order of a few tens of nanometers or below), standard silicide processes consume a major part of the Si in the junction. Also, for devices manufactured on thin SOI substrates, the amount of Si available for the silicide reaction is very limited. It is therefore necessary to devise a method to reduce consumption of the Si substrate.
In the current self-aligned cobalt silicide process, a TiN/Co film is deposited over the devices and annealed to form cobalt monosilicide over exposed Si regions (i.e., source, drain and gate) of the transistors. A selective wet etch is then performed to remove the TiN cap and the non-reacted cobalt left over the oxide or nitride regions. The cobalt monosilicide is then annealed to form the cobalt disilicide. The final cobalt disilicide formed is 3.5 times thicker than the initial cobalt film deposited and the reaction consumed an even thicker layer of Si (3.6 times the initial cobalt film) so that the surface of the silicide is slightly below the original Si surface.
Many options have been proposed to limit the Si consumption of the Si substrate. One strategy relied on the selection of different metal silicides that would form with a lower amount of Si consumption. This is the case in nickel monosilicide. Comparing the phases of the Ni—Si and Co—Si systems, one finds that the lowest resistivity phase for each system is NiSi and CoSi
2
. The lower concentration of Si in NiSi compared to CoSi
2
results in a lower consumption of Si for silicide formation with the same low sheet resistance. However, NiSi brings other concerns about the processing (that are non-existent with a CoSi
2
process) such as a major reduction in thermal budget after silicidation brought about by both the possible formation of higher resistivity NiSi
2
and the morphological stability of the film.
A second strategy for limiting substrate and junction consumption is to have a secondary source of Si. This had been proposed and can be done in many different ways. Each prior art method must be consistent with the self-aligned process. The Si can be added first to the exposed Si regions alone using selective epitaxy before metal deposition. It can also be deposited simultaneously with the metal in a selective chemical vapor deposition (CVD) process. More recently, it has been suggested that the Si be added during silicidation, after the selective etch of the non-reacted metal. The Si is deposited as a blanket film above cobalt monosilicide or the metal-rich silicide. During the second anneal of the process, the formation of CoSi
2
can at least in part come from the reaction with the top Si film helping in reducing Si consumption of the substrate.
Despite the advances made in this field, there is still a need for developing a new and improved self-aligned silicide process which is capable of substantially reducing Si consumption in shallow junction devices as well as thin SOI electronic devices.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a silicidation process which substantially reduces the amount of Si consumed in the source, drain and gate regions of semiconductor electronic devices during silicidation.
A further object of the present invention is to provide a self-aligned suicide process (i,e., salicide process) that includes materials and processing steps that are compatible with existing semiconductor device technologies.
An even further object of the present invention is to provide a method of forming an ohmic contact (i.e., a silicide region) that is present on the surface of Si in its lowest resistivity phase.
An additional object of the present invention is to provide a method of forming ohmic, contacts which does not necessarily increase the thermal budget of the process.
These and other objects and advantages art achieved in the present invention by employing a method which includes the use of a metal alloy layer and a blanket layer of Si. Specifically, one method of the present invention includes forming a first layer over a semiconductor wafer including at least exposed silicon-containing areas that are not covered by an insulator. The first layer comprises a M—Si G alloy, wherein M is Co, Ni or a combination of Co and Ni, where Si is less than 30 atomic % and Ge is less than 20 atomic %. Next, the first layer is subjected to a first annealing step which forms a metal rich silicide phase of Co
2
Si or Ni
x
Si
y
over the exposed silicon-containing areas, wherein x and y are integers in which x is greater than y and Ge is partly in solution and partly segregates out of the silicide phase. The segregated Ge functions to substantially reduce silicon diffusion from the silicon-containing areas to the silicide during phase transformations in a subsequent second annealing step. After performing the first annealing step, any ureacted M—Si—Ge-alloy present on the semiconductor wafer is etched and thereafter a blanket layer of Si is formed over the silicide and the semiconductor wafer. A second annealing is then performed which converts the metal rich silicide phase into its lowest resistance phase Any remaining non-reacted Si is then removed.
In another aspect of the preset invention a method of fob an ohmic contact to a SiGe alloy exposed in an opting trough an insulator is provided. Specifically, this method of the present invention includes forming a first blanket layer over a semiconductor wafer including at least an exposed Si—Ge alloy not covered by an insulator. In accordance with the present invention, the first layer comprises a M—Si alloy, wherein M is Co, Ni or a combination of Co and Ni, and Si is less than 30 atomic %. The first layer is then subjected to a first annealing step which forms a metal rich silicide phase of Co
2
Si or Ni
x
Si
y
, whew x and y are integers in which x>y. The SiGe alloy functions to substantially reduce Si diffusion from the SiGe alloy area to the silicide during phase transformations in a subsequent second annealing step. Any unreacted M—Si alloy present on the semiconductor wafer is then etched away and thereafter a blanket layer of Si Is formed over the silicide and the semiconductor wafer. A second annealing is then performed to convert the silicide into its lowest resistance silicide phase and thereafter any remaining non-reacted Si is removed. Note this aspect of the present invention differs from the previous aspect in that the metal alloy is M—Si, other than M—Si—Ge.
In both of the above-described methods wherein Co is employed; the first annealing step may form Co monosilicide rather than the metal rich silicide phase of Co. In this embodiment, the second annealing step converts Co monosilicide to Co disilicide.


REFERENCES:
patent: 5849630 (1998-12-01), Johnson
patent: 6187617 (2001-02-01), Gauthier, Jr. et al.
patent: 6323130 (2001-11-01), Brodsky et al.
patent: 6331486 (2001-12-01), Cabral, Jr. et al.
patent: 6346477 (2002-02-01), Kaloyeros et al.

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