Self-aligned shallow trench isolation

Details Self-aligned shallow trench isolation Self-aligned shallow trench isolation

2008-09-16

2008-09-16

Smith, Zandra (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S453000, C438S594000, C257SE21200, C257SE21206, C257SE21546, C257SE21642, C257SE21649

Reexamination Certificate

active

11282422

ABSTRACT:
A method of making a semiconductor structure includes etching an isolation oxide. The isolation oxide is in a substrate, a gate layer is on the substrate, a patterned metallic layer is on the gate layer, and a first patterned etch-stop layer is on the metallic layer.

REFERENCES:
patent: 5731241 (1998-03-01), Jang et al.
patent: 6235627 (2001-05-01), Nakajima
patent: 6680516 (2004-01-01), Blosse et al.
patent: 6835616 (2004-12-01), Ben-Tzur et al.
patent: 2004/0016956 (2004-01-01), Choi et al.
patent: 2006/0001112 (2006-01-01), Lee
Encyclopedia of Chemical Technology, Kirk-Othmer, vol. 14, pp. 677-709, (1995).

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