Self-aligned process for making contacts to silicon substrates d

Details Self-aligned process for making contacts to silicon substrates d Self-aligned process for making contacts to silicon substrates d

1997-01-21

1999-01-12

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

438620, 438622, 438634, 438623, 438624, 438637, 438666, 438671, 438740, 438734, 438736, H01L 21306

Patent

active

058588779

ABSTRACT:
A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multi-level metal integrated circuits.

REFERENCES:
patent: 5126006 (1992-06-01), Cronin et al.
patent: 5354711 (1994-10-01), Heitzmann et al.
C.W. Kaanta et al., "Dual Damascene: A ULSI Wiring Technology" VMIC Conference, Jun. 11-12, 1991, pp. 144-152.

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