Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-29
2001-08-21
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S279000
Reexamination Certificate
active
06277693
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming flash memory. More particularly, the present invention relates to a self-aligned process for forming the source lines of an ETOX flash memory.
2. Description of the Related Art
ETOX flash memory is a type of conventional erasable programmable read only memory (EPROM) that also includes a thin tunnel oxide layer in its structure. In fact, the name ETOX refers to an EPROM with a tunnel oxide layer.
FIG. 1
is a schematic top view of a portion of an ETOX flash memory structure.
FIG. 2A
is a cross-sectional view along line A-A′ of
FIG. 1
showing a unit memory cell of the ETOX flash memory, while
FIG. 2B
is a cross-sectional view along line B-B′ of FIG.
1
.
As shown in
FIGS. 1
,
2
A and
2
B, an ETOX flash memory structure is formed in several steps. First, longitudinal device isolation structures
110
are formed in a substrate
100
. In general, with a critical dimension larger than 0.25 &mgr;m, field oxide (FOX) is frequently used to form the device isolation structures
110
. However, for devices having a critical dimension smaller than 0.25 &mgr;m, shallow trench isolation (STI) structures are used more often. In the subsequent step, a tunnel oxide layer
120
, a floating gate
130
, an oxide
itride/oxide (ONO) composite dielectric layer
140
and a control gate
150
are sequentially formed over the substrate
100
. The floating gate
130
, the ONO dielectric layer
140
and the control gate
150
together constitute a stacked gate.
The device isolation structures
110
in the region for forming the desired source lines are removed and so trenches
190
are formed in the substrate
100
. Using the stacked gate as a mask, an ion implantation is carried out to implant ions into the exposed substrate
100
. Hence, a source line
160
and a drain terminal
170
are formed in the substrate
100
on each side of the gate stack.
Subsequent operation includes forming a bit line contact
180
above the drain terminal
170
for connecting the drain terminal
170
to the bit line (not shown) over the stacked gate. The bit lines run in a direction parallel to the device isolation structures
110
but perpendicular to the stacked gates. The source line
160
runs in a direction perpendicular to the device isolation structures
110
but parallel to the stacked gates. Since subsequent operations necessary for forming a complete ETOX flash memory should be familiar to persons skilled in the art of semiconductor manufacturing, detailed descriptions of the steps are omitted here.
In the aforementioned process of removing the device isolation structures
110
in preparation for implanting ions into the substrate
100
to form the source line, a number of problems are often encountered.
FIG. 3
is a cross-sectional view along line III-III′ of the source line
160
in FIG.
1
. In
FIG. 3
, cross-sectional structures of adjacent memory cells are also drawn. After the removal of device isolation structures
110
, trenches
190
are formed in the substrate
100
. The subsequent implantation of ions into the exposed substrate
100
results in the formation of source lines
160
. Since STI structures
110
are often used when critical dimension of device drops to below 0.25 &mgr;m, trenches
190
with high aspect ratio are formed after the device isolation structures
110
are removed. Hence, no matter at what angle the incoming ion beam is set, whether it comes from direction
200
a
,
200
b
or
200
c
, only a portion of the substrate surface of each trench
190
such as
195
a
,
195
b
or
195
c
, is doped. Unless the ion beam changes its angle of tilt and adjusts its implantation energy level continuously, doped ions cannot form a continuous conductive band that links regions like
195
a
,
195
b
and
195
c
in each trench
190
. Because continuous adjustment of the ion beam to form a uniformly doped substrate layer is a difficult process, most often than not, electrical resistivity of the source lines
160
rises and discontinuity problems intensify.
As resistivity of the source line
160
rises, operational speed of the ETOX flash memory drops. On the other hand, if the level of concentration of dopants in the substrate
100
is raised to increase the electrical conductivity of the source lines
160
, the band-to-band tunneling current may increase, resulting in a larger leakage current. Furthermore, a source line contact (not shown in the figure) must be erected for every 32 bits if the electrical resistivity of the source lines is too high. Hence, the ultimate level of integration for the ETOX flash memory is restricted.
SUMMARY OF THE INVENTION
The invention provides a self-aligned process for forming the source lines of an ETOX flash memory. A plurality of device isolation lines that are parallel to each other is formed in a substrate. A plurality of parallel stacked gates that are perpendicular to the device isolation lines is next formed over the substrate. Between two adjacent stacked gates is a region capable of accommodating at least one source line parallel to the stacked gates. A cap layer is formed over each stacked gate, and then spacers are formed over the sidewalls of the stacked gates. The device isolation structure within the source line region is removed, and then a conductive line is formed within the source line region of the substrate.
According to the self-aligned process of forming the source lines of an ETOX flash memory, the device isolation line within the source line region is removed before forming a conductive line to serve as the source line. A material having high electrical conductivity such as metal or doped polysilicon can be used to form the conductive line so that operational speed and the level of integration of the ETOX flash memory are increased.
In addition, if the conductive line is formed using doped polysilicon, a subsequent annealing operation can be carried out to drive the dopants within the doped polysilicon into the source line region of the substrate. Hence, a uniform and continuously doped source line is formed in the substrate under the conductive line.
Accordingly, the present invention provides a self-aligned process for forming the source lines of an ETOX flash memory capable of lowering electrical resistivity of the source lines.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5966602 (1999-10-01), Kawazu et al.
patent: 5998262 (1999-12-01), Chen
patent: 6013551 (2000-01-01), Chen et al.
patent: 6027971 (2000-02-01), Cho et al.
patent: 6103574 (2000-08-01), Iwasaki
Booth Richard
Huang Jiawei
J.C. Patents
Taiwan Semiconductor Manufacturing Co. Ltd.
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