Self-aligned process for fabricating memory cells with two...

Details Self-aligned process for fabricating memory cells with two... Self-aligned process for fabricating memory cells with two...

2002-05-23

2004-03-09

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S201000, C438S211000, C438S257000, C438S514000, C438S596000, C257S314000

Reexamination Certificate

active

06703298

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a self-aligned, scalable non-volatile memory (NVM) cell having two isolated floating gates in a single transistor. The present invention also relates to a method for fabricating such an NVM cell.
RELATED ART
FIG. 1
is a cross sectional view of a dual floating-gate transistor
12
. Dual floating-gate transistor
12
includes substrate
16
, source/drain regions
14
, channel region
20
, a pair of polysilicon floating gates
24
, bit line oxide regions
19
, isolation openings
27
, tunnel layer
15
, barrier layer
17
and control gate
26
. Dual floating-gate transistor
12
is capable of storing two bits of information in a non-volatile manner, one bit in each of the floating gates
24
.
A first photoresist mask is used to define the centrally located isolation opening
27
, and a second photoresist mask is used to define the adjacent isolation openings
27
, thereby isolating the polysilicon floating gates
24
. The use of photolithography for dividing the polysilicon floating gates
24
into two sections undesirably limits the possibilities for scaling down the dual floating-gate transistor
12
. Moreover, this process undesirably adds two masks to the process flow. Dual floating-gate transistor
12
is more fully described in U.S. Pat. No. 6,242,306 B1, issued to Pham et al.
FIG. 2
is a cross sectional view of a first double-density non-volatile memory cell
42
and a second double-density non-volatile memory cell
42
′. This double-density non-volatile memory cell pair includes P-type substrate regions
20
A-
20
C, N+ type source layer
21
, which includes source regions
21
A-
21
C, P type channel regions
33
, tunnel dielectric layer
34
, polysilicon floating gates
35
A-
35
B, P type impurity regions
52
, interpoly dielectric layer
60
, control gate electrodes
61
having tungsten silicide layer
62
formed thereon, drain regions
63
, oxide layer
70
, and bit-line through hole
71
.
A hard mask (which is likely patterned using a photoresist mask) is used to form the trenches in which the polysilicon floating gates
35
A-
35
B are located. Another photoresist mask is used to form the holes that extend through polysilicon floating gates
35
A-
35
B (i.e., the holes wherein the control gate electrodes
62
are formed). The control gate electrodes
62
are patterned in a conventional manner, which likely includes the formation of another photoresist mask. Bit line through hole
71
is subsequently etched, likely using yet another photoresist mask.
The use of photolithography for dividing the polysilicon floating gates
35
A-
35
B into two sections undesirably limits the possibilities for scaling down the dual floating-gate transistors
42
and
42
′. Moreover, this process undesirably uses a relatively large number of masks in the process flow. Double-density non-volatile memory cells
42
and
42
′ are more fully described in U.S. Pat. No. 6,232,632 B1, issued to Liu.
FIG. 3
is a cross sectional view of another conventional 2-bit non-volatile memory transistor
80
. Memory transistor
80
, which is fabricated in p-type substrate
82
, includes n+ source region
84
, n+ drain region
86
, channel region
87
, silicon oxide layer
88
, silicon nitride layer
90
, silicon oxide layer
92
, and control gate
94
. Oxide layer
88
, nitride layer
90
and oxide layer
92
are collectively referred to as ONO layer
91
. Memory transistor
80
includes a first charge trapping region
96
and a second charge trapping region
98
in silicon nitride layer
90
. Memory transistor
80
operates as follows. Charge trapping region
96
is programmed by connecting source region
84
to ground, connecting drain region
86
to a programming voltage of about 5 Volts, and connecting control gate
94
to a voltage of about 10 Volts. As a result, electrons are accelerated from source region
84
to drain region
86
. Near drain region
86
, some electrons gain sufficient energy to pass through oxide layer
88
and be trapped in charge trapping region
96
of nitride layer
90
in accordance with a phenomenon known as hot electron injection. Because nitride layer
90
is non-conductive, the injected charge remains localized within charge trapping region
96
in nitride layer
90
. Charge trapping region
98
is programmed in a reverse manner, by connecting drain region
86
to ground, connecting source region
84
to a programming voltage of about 5 Volts, and connecting control gate
94
to a voltage of about 10 Volts. Again, because nitride layer
90
is non-conductive, the injected charge remains localized within charge trapping region
98
in nitride layer
90
.
Charge trapping region
96
of memory transistor
80
is read by applying 0 Volts to drain region
86
, 2 Volts to source region
84
, and 3 volts to gate electrode
94
. If charge is stored in charge trapping region
96
(i.e., memory transistor
80
is programmed), then memory transistor
80
does not conduct current under these conditions. If there is no charge stored in charge trapping region
96
(i.e., memory transistor
80
is erased), then memory cell
80
conducts current under these conditions. Charge trapping region
98
of memory transistor
80
is read in a reverse manner, by applying 0 Volts to source region
84
, 2 Volts to drain region
86
, and 3 volts to gate electrode
94
.
Charge trapping region
96
is erased by applying 0 Volts to gate electrode
94
, 8 Volts to drain region
86
and 3 Volts to source region
84
. Charge trapping region
98
is erased in a similar manner, by applying 0 Volts to gate electrode
94
, 8 Volts to source region
84
, and 3 Volts to drain region
86
. Memory transistor
80
is described in more detail in U.S. Pat. No. 5,768,192 by Eitan.
During an erase operation of charge trapping region
96
, band-to-band tunneling of electrons takes place at the edge of drain region
86
. Generated holes are accelerated in the lateral field and are injected into ONO layer
91
. The centroid of the injected holes is shifted with respect to the centroid of the shifted electrons (i.e., there is a misalignment of electrons and holes in charge trapping region
96
). The holes, which are more mobile in silicon nitride layer
90
than the electrons, can shift laterally in silicon nitride layer. This results in threshold voltage instabilities, wherein the threshold voltage of the erased state increases at room temperature, and wherein the threshold voltage of the programmed state decreases during bakes.
Moreover, scaling of memory transistor
80
is limited due to electron/hole distributions coexisting in silicon nitride layer
90
. In the course of cycling (performed during endurance tests), some electrons are trapped far from drain region
86
. These electrons are mainly secondary and tertiary electrons created deep in substrate
82
. When the electron trapping occurs far from drain region
86
, it is difficult to erase the cell because the position of injected holes is fixed. In the erase procedure, the field of these electrons is compensated by the field of the holes. However, the electrons physically remain and influence the second bit. This effect is stronger in short channel devices.
Finally, silicon nitride layer
90
is charged with electrons during the process flow (i.e., plasma charging). The result is an increased level of threshold voltage and threshold voltage spread. The ONO structure
91
cannot be discharged by ultra-violet (UV) irradiation after processing has been completed, because the traps in silicon nitride have extremely low photoionization cross sections. Thus, UV irradiation would cause electrons to be injected into ONO layer
91
, thereby undesirably increasing the threshold voltage.
It would therefore be desirable to have a scalable non-volatile memory cell having a pair of isolated floating gates, wherein the non-volatile memory cell can be fabricated without requiring additional masks to be added to a conventional process flow. It would also be desirable to decrease threshold vo

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