Self-aligned process for a stacked gate RF MOSFET device

Details Self-aligned process for a stacked gate RF MOSFET device Self-aligned process for a stacked gate RF MOSFET device

2002-09-06

2004-05-18

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S217000, C438S592000

Reexamination Certificate

active

06737310

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate an RF metal oxide semiconductor field effect transistor (MOSFET), device, featuring a stacked metal gate structure, self-aligned to, and formed directly overlying, a polysilicon gate structure.
(2) Description of Prior Art
To achieve the objective of a system on a chip (SOC), comprised with various MOSFET type devices, the fabrication procedures for such MOSFET devices, such as baseband or digital, as well as RF type devices, have to be integrated. However the RF type MOSFET devices are designed to supply enhanced performance when compared to other MOSFET type devices of the SOC application, therefore the RF MOSFET devices have to be comprised with specific features that will enhance device performance. Reducing gate resistance, as well as reducing contact resistance for the RF MOSFET devices, can result in the desired performance enhancements. This invention will describe a process for integrating the higher performing RF MOSFET type devices, with digital type MOSFET type devices, for the SOC application, with the RF MOSFET type device featuring a metal gate contact structure, formed self-aligned to, and directly on, an underlying MOSFET gate structure, in a region in which the gate structure resides overlying a semiconductor active device region, therefore eliminating the gate resistance (Rg), increase experienced with counterpart designs in which contact to a gate structure is accomplished in a region away from the active device region, resulting in long and resistive paths. In addition this invention will feature larger openings to source/drain regions, thus reducing contact resistance (Rc), of the RF MOSFET device when compared to counterpart type devices fabricated with smaller openings to source/drain regions. Prior art, such as Givens et al, in U.S. Pat. No. 5,268,330, describe a method of forming a metal contact structure to an underlying polycide gate structure, however this prior art does not employ the novel procedure used to self-align the metal gate contact structure to an underlying polysilicon, or polycide structure.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a RF type, MOSFET device, for a system on chip (SOC), application.
It is another object of this invention to form a stacked gate structure for the RF type MOSFET device, comprised of a metal gate contact structure, formed self-aligned to, and directly on, an underlying MOSFET gate structure, in a region in which the gate structure resides on an active device region of the semiconductor substrate, to reduce gate resistance via direct current flow from an overlying metal interconnect structure through the stacked gate structure.
It is another object of this invention to form a dual damascene type, stacked gate trench shape, in a silicon oxide-silicon nitride-silicon oxide, composite layer, to accommodate the metal gate contact structure of the stacked gate structure, via creation narrow diameter openings in silicon nitride layer, to be used as an etch mask to define the narrow diameter opening of the dual damascene opening, with the narrow diameter openings in the silicon nitride layer formed via removal of a raised portion of the silicon nitride layer, in a region in which the silicon nitride layer directly overlaid the top surface of the gate structure.
It is still yet another object of this invention to increase the area of the RF type MOSFET source/drain contact openings via use of rectangular contact openings, to reduce the contact resistance, and this enhance device performance.
In accordance with the present invention a process of forming a stacked gate MOSFET structure for a RF type MOSFET device, featuring a metal gate contact structure component self-aligned to, and directly overlying the MOSFET polysilicon gate structure, in a region in which the gate structure resided overlying an active device region in the semiconductor substrate, is described. After formation of the MOSFET polysilicon gate structure, comprised with an overlying layer of metal silicide, comprised with silicon nitride spacers on the sides of the MOSFET gate structure, and comprised with a source/drain region located in an area of the semiconductor active device region not covered by the MOSFET polysilicon gate structure, a first silicon oxide layer is deposited, resulting in a raised portion of the first silicon oxide located only overlying the top surface of the MOSFET polysilicon gate structure. A thin silicon nitride layer is then deposited, contouring the raised, or bumped topography, of the underlying first silicon oxide layer. A chemical mechanical polishing (CMP), procedure is employed to remove the portion of the thin silicon nitride layer overlying the raised portion of first silicon oxide layer, resulting in a silicon nitride masking layer, now comprised with small diameter openings which expose regions of the first silicon oxide layer, in regions where the first silicon oxide layer directly overlays the top surface of the MOSFET polysilicon gate structures. After deposition of a second silicon oxide, a photoresist shape is used as an etch mask to define a large diameter opening in the second silicon oxide layer, exposing the silicon nitride masking layer, comprised with the small diameter openings. The etch process is continued to selectively remove portions of the first silicon oxide layer, exposed in the small diameter openings in the silicon nitride masking layer, resulting in a dual damascene opening, or stacked gate trench shape, comprised of a large diameter opening in the second silicon oxide layer, and a smaller diameter opening in the silicon nitride masking layer, and in the first silicon oxide layer, exposing a portion of the top surface of the MOSFET polysilicon gate structure, in a region in which the MOSFET polysilicon gate structure overlays an active device region. A metal layer is deposited and subjected to a CMP procedure, to create the metal gate contact structure, in the dual damascene opening, overlying the MOSFET polysilicon gate structure in a region in which the MOSFET polysilicon gate structure overlays an active device region. A metal interconnect structure is then formed on the metal gate contact structure, resulting in vertical current flow from the metal interconnect structure to MOSFET, stacked gate structure, reducing gate resistance when compared to counterparts in which contact to the MOSFET polysilicon gate structure is accomplished over non-active device areas, requiring long, resistive polysilicon gate lengths.
Rectangular shaped, contact hole openings, are also formed to the source/drain region of the RF type MOSFET device, to allowing for larger contact regions, thus reducing source/drain contact resistance, when compared to counterparts fabricated with smaller area, non-rectangular, contact hole openings.


REFERENCES:
patent: 5268330 (1993-12-01), Givens et al.
patent: 6037223 (2000-03-01), Su et al.
patent: 6063675 (2000-05-01), Rodder
patent: 6069047 (2000-05-01), Wanlass
patent: 2003/0008450 (2003-01-01), Tsai et al.

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