Self-aligned pocket process for deep sub-0.1 .mu.m CMOS devices

Details Self-aligned pocket process for deep sub-0.1 .mu.m CMOS devices Self-aligned pocket process for deep sub-0.1 .mu.m CMOS devices

1998-06-16

2000-07-25

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438563, 438564, 438596, H01L 21336

Patent

active

06093610&

ABSTRACT:
A self-aligned pocket process for formation of CMOS devices and the devices by means of a sidewall doped overlayer to achieve deep sub-0.1 .mu.m CMOS with reduced gate length variation. The localized pocket results in reduced C.sub.J. The method includes providing a semiconductor substrate and forming a gate electrode over the substrate separated from the substrate by an electrical insulator. A preferably electrically insulating sidewall material which contains a dopant of predetermined conductivity type is formed over and either in contact with or spaced from the sidewalls of the gate electrode. The dopant is caused to migrate into the substrate beneath the sidewall material with some lateral movement to form a pocket of the predetermined conductivity type in the substrate. A further sidewall can be added to the sidewall material after pocket formation. The sidewall material can be later removed. Drain extensions and/or source/drain regions are formed in the substrate of conductivity type opposite the predetermined conductivity type, with or without use of sidewalls as a mask to provide minimal overlap between the drain extensions and/or source/drain regions and the pocket.

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"Sub-50 NM Gate Length N-MOSFETS with 10 NM Phosphorus Source and Drain Junctions", Ono et al., 1993 IEEE, pp. 119-122.

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