Self-aligned patterning method by using non-conformal film...

Details Self-aligned patterning method by using non-conformal film... Self-aligned patterning method by using non-conformal film...

2011-03-15

2011-03-15

Pham, Thanh V (Department: 2894)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C257S314000, C257S315000

Reexamination Certificate

active

07906395

ABSTRACT:
A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.

REFERENCES:
patent: 6159801 (2000-12-01), Hsieh et al.
patent: 6555427 (2003-04-01), Shimizu et al.
patent: 7067377 (2006-06-01), Park et al.
patent: 2007/0001211 (2007-01-01), Lee

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