Self-aligned non-volatile process with differentially grown gate

Details Self-aligned non-volatile process with differentially grown gate Self-aligned non-volatile process with differentially grown gate

1996-09-27

1998-05-12

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438766, 438770, H01L 21336

Patent

active

057504288

ABSTRACT:
A method of fabricating a novel electrically erasable programmable read only memory (EEPROM) cell for use in semiconductor memories is disclosed herein. Since the degree of ion implantation in the substrate determines the thichness of the silicon dioxide. The proper thickness of the silicon dioxide can be determined by considering the particular dopant to be used and degree of ion implantation, a 50-100 angstroms silicon dioxide is chosen for an arsenic or phosphorus dopant, 1E14-1E15 atoms/cm.sup.2, 100 KeV, ion implantation. A 150-350 angstroms silicon dioxide is chosen for an arsenic or phosphorus dopant, 1E11-1E13 atoms/cm.sup.2, 100 KeV, ion implantation. The method includes the steps of: forming an isolation layer on a substrate to serve as an isolation; doping ions to form a lightly-doped region in the substrate; patterning a photoresist on the substrate; doping an ions to form a highly-doped region in the substrate; removing the photoresist; oxidizing the substrate to form a gate oxide and a tunnel oxide simultaneously; and forming a first polysilicon layer on the gate oxide and the tunnel oxide.

REFERENCES:
patent: 5393684 (1995-02-01), Ghezzi
patent: 5429960 (1995-07-01), Hong

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