Self-aligned MOSFET with electrically active mask

Details Self-aligned MOSFET with electrically active mask Self-aligned MOSFET with electrically active mask

1996-12-18

2002-04-16

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S149000, C438S166000, C438S795000, C257S057000, C257S066000, C257S347000, C257S352000, C257S410000, C257S411000, C257S412000

Reexamination Certificate

active

06372592

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the fabrication of MOSFETs. More specifically, but without limitation thereto, the present invention relates to the fabrication of an electrically active MOSFET gate that may serve to mask laser radiation during annealing to form a self-aligned semiconductor structure.
The recent growth in the personal communications market has produced a rise in interest in inexpensive low power, high frequency, low noise electronic devices and circuits.
FIG. 1
shows a model of a FET typically used to predict high frequency performance. In making a FET it is desirable to reduce the series resistance of the gate, source, and drain, shown respectively as Rg, Rs, and Rd, and to keep the gate-to-drain capacitance Cgd as low as possible in order to reduce device noise and to improve high frequency performance. Rg, Rs, Rd, and Cgd are known as parasitic resistance and capacitance.
Three typical FET structures are diagrammed in FIG.
2
. Dopants are typically incorporated into a semiconductor or a semiconductor alloy by ion implantation, diffusion, gas immersion techniques, and the like to form source and drain regions in a FET structure. However, dopant incorporation disrupts the crystalline structure of the semiconductor or alloy. Annealing the semiconductor structure corrects the damage and places the dopants in electrically active crystal sites. Annealing, also called activation of the implant, is well known in the art of microelectronic fabrication. The method usually used to activate an implant is to heat the entire substrate to a high temperature for a given period of time.
In the FET structure of FIG.
2
(
a
), gate
204
overlaps source
202
and drain
206
. Gate
204
comprises a gate insulator
210
and a gate conductive layer
208
. The increased contact area reduces the parasitic resistances, but also increases the gate-to-drain capacitance. Another problem with this structure is that the most important parameter affecting FET performance, the gate length L
g
, is relatively large, while optimum (high-speed) performance is achieved by making the gate length as small as possible.
In FIG.
2
(
b
), the gate-to-drain capacitance has been reduced by reducing the gate length below the distance separating the source and drain regions. However, the gap between source
202
and drain
206
has been increased to relieve the mask alignment constraints, which increases Rs and Rd.
A solution to the problem of reducing Cgd, Rg, and Rd while still satisfying the mask alignment constraints is to use a self-aligned process as in FIG.
2
(
c
). In a self-aligned process, the gate is used as a mask during the source and the drain implanting. In the structures of FIG.
2
(
a
) and FIG.
2
(
b
), a separate photolithographic mask alignment step is typically required for the ion implants and the gate. By using a self-aligned process, shorter gate lengths may be fabricated while reducing the separation between source
202
and drain
206
to the gate length L
g
, thus reducing the source and drain resistances.
Selecting a suitable material for gate conductive layer
208
poses a problem for the self-aligned process, however. A highly conductive metal such as aluminum or gold would be desirable in a self-aligned FET gate to reduce the gate series resistance Rg, but the high temperatures required for the source and drain implant activations (typically well above 500° C.) would cause aluminum and gold to melt. Materials typically used for conductive layer
208
in a self-aligned process therefore have higher melting temperatures than most metals. Examples of such conductive layer materials are refractory metals such as doped polycrystalline silicon, titanium silicide, platinum silicide, tungsten silicide, and the like. The problem with using polysilicon or other refractory metals is that they have a higher resistivity than the lower melting temperature metals. As a result, Rg is increased, which causes a degradation of transistor performance. The refractory metals may be used, however, for the source and drain regions to reduce series resistance Rs.
While group III-V semiconductors have dominated the field of devices and circuitry in the personal communications market, silicon-on-insulator (SOI) materials, including silicon-on-sapphire (SOS), have recently been demonstrated as a lower cost alternative. SOI materials are preferable to bulk silicon for such applications due to their reduced parasitic capacitance. However, complex fabrication techniques are required to reduce the gate resistance in the typical case of a T-gate structure
30
illustrated in FIG.
3
. The complexity of fabricating T-gate
310
in
FIG. 3
is shown by the steps depicted in FIG.
4
. T-gate
310
comprises a sidewall oxide
320
, a barrier layer
330
, a conductive layer
340
, and a gate metal
350
.
FIG.
4
(
a
) shows a cross-section of a self-aligned FET formed by siliciding source, drain, and gate regions
412
, depositing oxide
414
, and forming a planar resist layer
416
. In FIG.
4
(
b
), planar resist layer
416
and oxide layer
414
have been etched to expose the top of T-gate
310
. This is followed by etching contact holes
432
in oxide
414
, and deposition and patterning of final metallization
418
as illustrated in FIG.
4
(
c
).
The above description is a simplified version of the actual steps in the fabrication of a microelectronic device. Even the simplest patterning involves numerous steps that are time consuming, labor intensive, and have an associated yield, or failure rate. In a typical example of patterning, a semiconductor wafer is dipped in a solution to prime the surface and to increase adhesion of the photoresist. Photoresist, a light-sensitive polymer, is then spin-cast on the wafer and subjected to a hot plate bake to eliminate solvents. The photoresist is cured by annealing and exposed to light passed through a lithographic pattern on a mask or reticle using projection or contact photolithography apparatus. The exposed photoresist is developed by immersion in one or more chemical baths, then rinsed and dried. In some cases, additional ultraviolet (UV) light curing is required to harden the photoresist to withstand subsequent processing. The wafer containing the photoresist is subjected to etching by well known methods such as wet chemical, plasma/reactive-ion assisted, and laser-assisted etching to transfer the photolithographic pattern to the underlying layer. The patterned photoresist is then removed using, for example, wet chemical processing, plasma-assisted cleaning, or a combination of these. The structure of T-gate
310
in
FIG. 3
requires several such patterning steps.
Any reduction or elimination of steps in the fabrication process to increase yield is highly desirable because there is a corresponding reduction in cost, particularly in the final steps of the fabrication process where the semiconductor manufacturer already has a substantial investment in the wafer components. Improvements or refinements in the step of FET gate metallization are therefore especially cost effective.
Laser activation of ion implanted dopants has been recognized as an alternative to conventional furnace annealing, and techniques such as Gas Immersion Laser Doping (GILD) have proven valuable in the forming of shallow junctions in bulk silicon. See, for example, “Gas Immersion Laser Diffusion (GILDing)”, R. J. Pressley,
Taser Processing of Semiconductor Devices
, Proc. SPIE, Vol. 385, p. 30 (1983).
Thermally-assisted pulsed laser annealing of SOS was reported in “Thermally-Assisted Pulsed-Laser Annealing of SOS”, M. Yamada et al.,
Laser and Electron
-
Beam Tnteractions with Solids and Materials Processing
, Mat. Res. Soc. Symp. Proc., Vol. 1, pp. 503-510 (1981). Using Raman spectroscopy they measured the residual strain in annealed SOS due to the lattice mismatch between silicon and sapphire.
Continuous wave (CW) laser annealing of ion implanted oxidized silicon layers on sapphire was reported in “CW Laser Annealing of Ion Implanted Oxidized Silic

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