Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-04-24
2007-04-24
Baumeister, B. William (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S317000, C257SE29304
Reexamination Certificate
active
11070079
ABSTRACT:
A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface, and the channel region therebetween includes a first portion extending vertically along the trench sidewall and a second portion extending horizontally along the substrate surface. The floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. The control gate is disposed over and insulated from the channel region second portion. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge. The channel region second portion extends from the second region in a direction toward the sharp edge and the floating gate to define a path for programming the floating gate with electrons via hot electron injection.
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Hayashi, Fumihiko and Plummer, James D., “A Self-Aligned Split-Gate Flash EEPROM Cell With 3-D Pillar Structure”, 1999 Symposium on VLSI Technology Digest of Technical Papers, Center for Integrated System, Stanford University, Stanford, CA 94305, USA, pp. 87-88.
Chen Bomy
Lu Wen-Juei
Tsui Ying Kit
Baumeister B. William
DLA Piper (US) LLP
Movva Amar
Silicon Storage Technology, Inc.
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