Self aligned method of forming a semiconductor memory array...

Details Self aligned method of forming a semiconductor memory array... Self aligned method of forming a semiconductor memory array...

2006-12-05

2006-12-05

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S315000

Reexamination Certificate

active

07144778

ABSTRACT:
A self aligned method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench, and the channel region includes a first portion that extends vertically along a sidewall of the trench and a second portion that extends horizontally along the substrate surface. An electrically conductive floating gate is formed over and insulated from a portion of the channel region. A raised source line of conductive material is disposed over the source region, and laterally adjacent to and insulated from the floating gate. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion formed over but insulated from the floating gate.

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