Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-01-30
2004-08-10
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000, C438S267000, C438S593000, C438S594000
Reexamination Certificate
active
06773989
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a self-aligned method of forming a semiconductor memory array of floating gate memory cells of the split gate type. The present invention also relates to a semiconductor memory array of floating gate memory cells of the foregoing type.
BACKGROUND OF THE INVENTION
Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type, or a combination thereof.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the design rule of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, the present invention uses the technique of self-alignment to achieve the manufacturing of a semiconductor memory array of the floating gate memory cell type.
In the split-gate architecture, the control-gate FET is known to play a major role in disturbing mirror cells, as well as affecting the programming injection efficiency for source-side-injection FLASH cells. A good process control on the Lcg (also called the WL (word-line) poly length, which is the length of the control or select gate that is disposed over the channel) can ensure a full turn-off of the control-gate device, and hence can effectively prevent any disturbance in a mirror cell during programming (program disturb). The present invention is a method to realize a self aligned FLASH cell with improved full turn-off of the control-gate device with better program disturb characteristics. The present invention is also such a device.
SUMMARY OF THE INVENTION
In the present invention, the WL (control/select gate) poly length is controlled by a photo lithography process, which provides excellent scalability and control over the WL poly length as compared to a WL poly formed by a spacer process. Since the tight control on the photo process is a by-product of logic technology, the present invention thus offers a better control on WL poly length, and hence a better suppression of program disturb in mirror cells. An additional advantage of the present invention is that it allows the formation of cells with different WL poly lengths on the same wafer.
The present invention also results in the formation of the WL poly having a substantially rectilinear shape or planar side wall portion, which makes it easier and more controllable to form the side wall spacer, and to address issues of WL-to-BL (Bit Line) & WL-to-source block shorts. Further, in the first embodiment of the present invention, the WL poly is defined by a WL trench rather than by a spacer etch. Thus, the memory cell is immune from WL-WL shorts due to isolation or trench oxide-to-active topography, and the WL poly has a flat surface which makes contact formation on the WL strap easier (no WL strap needed). The first embodiment further presents an advantage over prior art in that it enables to the option to perform “after development inspection” for critical dimension inspection, e.g. after the photo lithography definition of the WL dimension. If the control on the critical dimension WL is off target, the error can be detected and the wafer can be re-worked to correctly define this critical dimension.
The present invention is a self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, where each memory cell has a floating gate, a first terminal, a second terminal with a channel region therebetween, and a control gate. The method includes the steps of:
a) forming a plurality of spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, the active regions each comprising a first layer of insulation material on the semiconductor substrate and a first layer of conductive material on the first layer of insulation material;
b) forming a plurality of spaced apart first trenches across the active regions and isolation regions which are substantially parallel to one another and extend in a second direction that is substantially perpendicular to the first direction and exposing the first layer of the conductive material in each of the active regions, each of the first trenches having an upper portion and a lower portion wherein the upper portion has a greater width than that of the lower portion;
c) forming a second layer of insulation material in each of the active regions that is disposed adjacent to and over the first layer of conductive material;
d) filling each of the first trenches with a second conductive material to form blocks of the second conductive material, wherein for each of the blocks in each active region:
the block is adjacent to the second layer of insulation material and is insulated from the substrate, and
the block includes a protruding portion formed by the wider upper portion of the first trench that is disposed over the second layer of insulation material and the first layer of conductive material;
e) forming a plurality of first terminals in the substrate, wherein in each of the active regions each of the first terminals is adjacent to one of the blocks; and
f) forming a plurality of second terminals in the substrate, wherein in each of the active regions each of the second terminals is spaced apart from the first terminals and is below the first layer of conductive material.
In another aspect of the present invention for the self-aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, the method includes the steps of:
a) forming a plurality of spaced apart isolation regions on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, the active regions each comprising a first layer of insulation material on the semiconductor substrate and a first layer of conductive material on the first layer of insulation material;
b) forming a plurality of spaced apart first trenches across the active regions and isolation regions which are substantially parallel to one another and extend in a second direction that is substantially perpendicular to the first direction and exposing the first layer of the conductive material in each of the active regions, each of the first trenches having a side wall with an indentation formed therein;
c) forming a second layer of insulation material in each of the active regions that is disposed adjacent to and over the first layer of conductive material;
d) filling each of the first trenches with a second conductive material to form blocks of the second conductive material, wherein for each of the blocks in each active region:
the block is adjacent to the second layer of insulation material and is insulated from the substrate, and
the block includes a protruding portion formed by the indentation in the first trench side wall that is disposed over the second layer of insulation material and the first layer of conductive material;
e) forming a plurality of first terminals in the substrate, wherein in each of the active regions each of the first terminals is adjacent to one of the blocks; and
f) forming a plurality of second terminals in the substrate, wherein in each of the active regions each of the second terminals is
Gray Cary Ware & Freidenrich LLP
Quach T. N.
Silicon Storage Technology, Inc.
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