Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-14
2004-03-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S259000
Reexamination Certificate
active
06706592
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of forming an array of semiconductor non-volatile memory cells on a semiconductor substrate.
BACKGROUND OF THE INVENTION
Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type, or a combination thereof.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the design rule of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, self alignment minimizes the number of masking steps necessary to form memory cell structures, and enhances the ability to scale such structures down to smaller dimensions.
In the manufacture of memory cell arrays, it is also known to form a pointed edge on the floating gate that faces the control gate, to enhance the erase operation of the memory cell through Fowler-Nordheim tunneling. However, it can be difficult to form floating gate pointed edges having the desired sharpness. Moreover, the sharpness of the floating gate edges can be compromised by subsequent processing steps, such as over-etch processing steps needed to remove residual material (e.g. poly stringers). While there are many processing steps that could be added to form and help maintain the floating gate pointed edge, it is essential to streamline the manufacturing process (minimize material layers, masking steps and etch steps) in order to reduce manufacturing costs and defects, and increase yield.
There is a need for a manufacturing method that efficiently forms non-volatile memory cells with erase enhancing pointed edges, while still minimizing the number of processing steps necessary to reliably manufacture the non-volatile memory cells.
SUMMARY OF THE INVENTION
The present invention provides an improved method of manufacturing an array of semiconductor memory cells, which includes the steps of forming a plurality of spaced apart isolation regions on the substrate of a first conductivity type which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, forming a plurality of spaced apart blocks of conductive material in each of the active regions, wherein each of the conductive material blocks is disposed over and insulated from the substrate, forming a plurality of spaced apart first trenches in a first material in each of the active regions, wherein the conductive material blocks are disposed in the first trenches, etching away a top portion of the conductive material block in each of the first trenches to form sloping portions of the conductive material block therein that terminate in edges extending along sidewalls of the first trenches, removing the first material, forming a plurality of control gates of conductive material each disposed adjacent to and insulated from one of the conductive material blocks, and forming a plurality of spaced apart first and second regions in the substrate in each of the active regions that have a second conductivity type, with channel regions of the substrate defined between the first and second regions. Each of the control gates is disposed over and insulated from a portion of one of the channel regions.
Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.
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U.S. patent application Ser. No. 09/401,622, Johnson, filed Sep. 22, 1999.
Chern Geeng-Chuan Michael
Su Chien-Sheng
Grary Cary Ware & Freidenrich LLP
Le Thao P.
Nelms David
Silicon Storage Technology, Inc.
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