Self-aligned method of fabricating terrace gate DMOS transistor

Details Self-aligned method of fabricating terrace gate DMOS transistor Self-aligned method of fabricating terrace gate DMOS transistor

1997-04-15

1999-03-09

Booth, Richard A.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438585, 438975, 148DIG126, H01L 21336

Patent

active

058799940

ABSTRACT:
An active mask is used to etch field oxide in active areas down to an n- epitaxial substrate. After gate oxide growth, a polysilicon layer is deposited and planarized. The active mask defines the polysilicon gate critical dimension for a terrace gate DMOS structure. The edges of the polysilicon gates are self-aligned to the edges of the thick terrace gate oxide. Because no interlayer alignment is required to delineate the polysilicon gate, the design need not provide for alignment tolerance. A non-critical mask is deposited overlapping the terrace oxide. An etch back to field oxide in exposed areas is performed. An oxide-selective etch is performed to reduce the oxide thickness in source regions. Self-aligned body implantation, body contact masking and implantation, and source masking and implantation are performed. A dielectric is deposited. A source contact mask is deposited and a contact etch is performed. Source metal is deposited, and passivation layer is formed. Gate-drain capacitance caused by polysilicon gate overlap of the substrate is minimized as the overlap is minimized. Because input capacitance is reduced, switching speed is increased. This self-aligned feature also results in a smaller cell pitch dimension and higher packing density. Therefore, the specific ON resistance is reduced and current driving capacity is also greatly elevated.

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